+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
-import m5
from m5.objects import *
+from base_config import *
-class MyCache(BaseCache):
- assoc = 2
- block_size = 64
- latency = '1ns'
- mshrs = 10
- tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
- is_top_level = True
-
-cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
- MyL1Cache(size = '256kB'),
- MyCache(size = '2MB', latency='10ns'))
-system = System(cpu = cpu,
- physmem = PhysicalMemory(),
- membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
-cpu.connectAllPorts(system.membus)
-cpu.clock = '2GHz'
-
-root = Root(full_system=False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing',
+ cpu_class=TimingSimpleCPU).create_root()