sparc: update long regressions

[gem5.git] / tests / configs / simple-timing.py

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 8be0c0b3bae5e5b231f533ee17bf1ebf8050e132..bc9d016c5b07e917badd2fe2ea9c47b8182c25e9 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -32,18 +32,22 @@ from m5.objects import *
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    latency = 1
+    latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 5
 
-cpu = TimingSimpleCPU()
-#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-#                              MyCache(size = '2MB'))
+class MyL1Cache(MyCache):
+    is_top_level = True
 
+cpu = TimingSimpleCPU(cpu_id=0)
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB', latency='10ns'))
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
+cpu.clock = '2GHz'
 
 root = Root(system = system)