mem: Update DDR3 and DDR4 based on datasheets

[gem5.git] / tests / configs / tgen-simple-dram.py

diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index b57817c95e78b037e095cea4c5ac283bdba01641..d0d26e1f37ed515d00909b9cb5d11dd866329fd4 100644 (file)
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -49,7 +49,10 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
-                membus = NoncoherentBus(width = 16))
+                membus = NoncoherentBus(width = 16),
+                clk_domain = SrcClockDomain(clock = '1GHz',
+                                            voltage_domain =
+                                            VoltageDomain()))
 
 # add a communication monitor
 system.monitor = CommMonitor()