misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

[gem5.git] / tests / gem5 / x86-boot-tests / system / caches.py

diff --git a/tests/gem5/x86-boot-tests/system/caches.py b/tests/gem5/x86-boot-tests/system/caches.py
index 2c2e520e777fb5849e2149d180ef6415cf095fd1..80648bcf78738a7fd4f9fdfbe44afe0d8d8a2aa3 100755 (executable)
--- a/tests/gem5/x86-boot-tests/system/caches.py
+++ b/tests/gem5/x86-boot-tests/system/caches.py
@@ -113,8 +113,8 @@ class MMUCache(Cache):
         """
         self.mmubus = L2XBar()
         self.cpu_side = self.mmubus.master
-        for tlb in [cpu.itb, cpu.dtb]:
-            self.mmubus.slave = tlb.walker.port
+        cpu.mmu.connectWalkerPorts(
+            self.mmubus.slave, self.mmubus.slave)
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""