---------- Begin Simulation Statistics ----------
-host_inst_rate 1159099 # Simulator instruction rate (inst/s)
-host_mem_usage 201888 # Number of bytes of host memory used
-host_seconds 1397.12 # Real time elapsed on the host
-host_tick_rate 1828142910 # Simulator tick rate (ticks/s)
+host_inst_rate 759916 # Simulator instruction rate (inst/s)
+host_mem_usage 204700 # Number of bytes of host memory used
+host_seconds 2130.98 # Real time elapsed on the host
+host_tick_rate 851601124 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1619398860 # Number of instructions simulated
-sim_seconds 2.554133 # Number of seconds simulated
-sim_ticks 2554132875000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses)
+sim_insts 1619365942 # Number of instructions simulated
+sim_seconds 1.814744 # Number of seconds simulated
+sim_ticks 1814744167000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses
system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 606644555 # number of overall hits
+system.cpu.dcache.overall_hits 606642715 # number of overall hits
system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
system.cpu.dcache.overall_misses 506099 # number of overall misses
system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 439707 # number of replacements
system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4094.900260 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 308507 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1186515973 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1645653.221914 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1186516694 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 1186515973 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 721 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 1186516694 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1925902841 # number of overall hits
+system.cpu.icache.overall_hits 1186515973 # number of overall hits
system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 721 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use
-system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 659.165920 # Cycle average of tags in use
+system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 82097 # number of replacements
system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 16488.807758 # Cycle average of tags in use
system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61702 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5108265750 # number of cpu cycles simulated
-system.cpu.num_insts 1619398860 # Number of instructions executed
-system.cpu.num_refs 607161871 # Number of memory references
+system.cpu.numCycles 3629488334 # number of cpu cycles simulated
+system.cpu.num_insts 1619365942 # Number of instructions executed
+system.cpu.num_refs 607148814 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff