---------- Begin Simulation Statistics ----------
-host_inst_rate 1934138 # Simulator instruction rate (inst/s)
-host_mem_usage 214132 # Number of bytes of host memory used
-host_seconds 70.39 # Real time elapsed on the host
-host_tick_rate 2914099932 # Simulator tick rate (ticks/s)
+host_inst_rate 683746 # Simulator instruction rate (inst/s)
+host_mem_usage 213692 # Number of bytes of host memory used
+host_seconds 199.11 # Real time elapsed on the host
+host_tick_rate 1021439068 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
-sim_seconds 0.205117 # Number of seconds simulated
-sim_ticks 205116920000 # Number of ticks simulated
+sim_seconds 0.203377 # Number of seconds simulated
+sim_ticks 203376692000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107271 # number of writebacks
-system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
-system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 136106788 # number of overall hits
+system.cpu.icache.overall_hits 134366560 # number of overall hits
system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use
-system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use
+system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.replacements 120486 # number of replacements
system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 19319.557750 # Cycle average of tags in use
system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 87413 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 410233840 # number of cpu cycles simulated
+system.cpu.numCycles 406753384 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
projects / gem5.git / blobdiff