---------- Begin Simulation Statistics ----------
-host_inst_rate 154101 # Simulator instruction rate (inst/s)
-host_mem_usage 217652 # Number of bytes of host memory used
-host_seconds 11181.42 # Real time elapsed on the host
-host_tick_rate 57496303 # Simulator tick rate (ticks/s)
+sim_seconds 0.483463 # Number of seconds simulated
+sim_ticks 483463019500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1723073854 # Number of instructions simulated
-sim_seconds 0.642891 # Number of seconds simulated
-sim_ticks 642890553000 # Number of ticks simulated
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 223193937 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 259593204 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 340 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 18005065 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 242843937 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 296310364 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 17771313 # Number of times the RAS was used to get a target.
-system.cpu.commit.branchMispredicts 18004568 # The number of times a branch was mispredicted
-system.cpu.commit.branches 213462366 # Number of branches committed
-system.cpu.commit.bw_lim_events 57604302 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.commitCommittedInsts 1723073872 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 458 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 488146148 # The number of squashed insts skipped by commit
-system.cpu.commit.committed_per_cycle::samples 1166659925 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.476929 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.106061 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 510754561 43.78% 43.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 303447125 26.01% 69.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 123940356 10.62% 80.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 73811223 6.33% 86.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 36743344 3.15% 89.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 32005168 2.74% 92.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15998188 1.37% 94.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12355658 1.06% 95.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 57604302 4.94% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1166659925 # Number of insts commited each cycle
-system.cpu.commit.count 1723073872 # Number of instructions committed
-system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
-system.cpu.commit.loads 485926772 # Number of loads committed
-system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.refs 660773819 # Number of memory references committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.committedInsts 1723073854 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1723073854 # Number of Instructions Simulated
-system.cpu.cpi 0.746214 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.746214 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 65 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 27333.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits 62 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 82000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.046154 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses 501584612 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15160.364798 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11507.023204 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 493452712 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 123282570500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.016212 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 8131900 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 482613 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 88020523000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.015250 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7649287 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 63 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 63 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23758.689113 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20868.683162 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 168021895 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 108438268431 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.026446 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 4564152 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 2672149 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 39483611148 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1892003 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3136.287441 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20750 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 69.327600 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 24979 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 78341324 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 166000 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 674170659 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18251.409094 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 661474607 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 231720838931 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.018832 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 12696052 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 3154762 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 127504134148 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.014153 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9541290 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4087.096656 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997826 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 674170659 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18251.409094 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13363.406222 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 661474607 # number of overall hits
-system.cpu.dcache.overall_miss_latency 231720838931 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.018832 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 12696052 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 3154762 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 127504134148 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.014153 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9541290 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9537194 # number of replacements
-system.cpu.dcache.sampled_refs 9541290 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.096656 # Cycle average of tags in use
-system.cpu.dcache.total_refs 661474732 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 5035189000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 3122149 # number of writebacks
-system.cpu.decode.BlockedCycles 127119222 # Number of cycles decode is blocked
-system.cpu.decode.BranchMispred 630 # Number of times decode detected a branch misprediction
-system.cpu.decode.BranchResolved 46145837 # Number of times decode resolved a branch
-system.cpu.decode.DecodedInsts 2344585205 # Number of instructions handled by decode
-system.cpu.decode.IdleCycles 578307676 # Number of cycles decode is idle
-system.cpu.decode.RunCycles 449658106 # Number of cycles decode is running
-system.cpu.decode.SquashCycles 70439042 # Number of cycles decode is squashing
-system.cpu.decode.SquashedInsts 2261 # Number of squashed instructions handled by decode
-system.cpu.decode.UnblockCycles 11574920 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+host_inst_rate 167165 # Simulator instruction rate (inst/s)
+host_tick_rate 46903472 # Simulator tick rate (ticks/s)
+host_mem_usage 214756 # Number of bytes of host memory used
+host_seconds 10307.62 # Real time elapsed on the host
+sim_insts 1723073849 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 296310364 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 276394619 # Number of cache lines fetched
-system.cpu.fetch.Cycles 469857260 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 5099612 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2155595751 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 18544487 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.230452 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 276394619 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 240965250 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.676487 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1237098966 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.930612 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.884681 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.numCycles 966926040 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 767241756 62.02% 62.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 33244799 2.69% 64.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 58987586 4.77% 69.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 61314807 4.96% 74.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 46983054 3.80% 78.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 54993105 4.45% 82.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 53020195 4.29% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18334456 1.48% 88.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 142979208 11.56% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1237098966 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 39 # number of floating regfile reads
-system.cpu.fp_regfile_writes 31 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 276394619 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34658.288770 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34406.030856 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 276393684 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 32405500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 935 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 24531500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 713 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 387648.925666 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued
+system.cpu.iq.rate 2.087542 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 18504 # number of nop insts executed
+system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238650211 # Number of branches executed
+system.cpu.iew.exec_stores 191202715 # Number of stores executed
+system.cpu.iew.exec_rate 2.054022 # Inst execution rate
+system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1288034280 # num instructions producing a value
+system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle
+system.cpu.commit.count 1723073867 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 660773817 # Number of memory references committed
+system.cpu.commit.loads 485926771 # Number of loads committed
+system.cpu.commit.membars 62 # Number of memory barriers committed
+system.cpu.commit.branches 213462365 # Number of branches committed
+system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
+system.cpu.commit.function_calls 13665177 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 2977240585 # The number of ROB reads
+system.cpu.rob.rob_writes 4444170390 # The number of ROB writes
+system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
+system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads
+system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes
+system.cpu.fp_regfile_reads 117 # number of floating regfile reads
+system.cpu.fp_regfile_writes 59 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads
+system.cpu.misc_regfile_writes 126 # number of misc regfile writes
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use
+system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits
+system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 285044064 # number of overall hits
+system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses
+system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 1014 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 276394619 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34658.288770 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
-system.cpu.icache.demand_hits 276393684 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 32405500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 935 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 24531500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 713 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 577.423416 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.281945 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 276394619 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34658.288770 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34406.030856 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 276393684 # number of overall hits
-system.cpu.icache.overall_miss_latency 32405500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 935 # number of overall misses
-system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 24531500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 713 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 8 # number of replacements
-system.cpu.icache.sampled_refs 713 # Sample count of references to valid blocks.
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 577.423416 # Cycle average of tags in use
-system.cpu.icache.total_refs 276393684 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 48682141 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.branchMispredicts 19351943 # Number of branch mispredicts detected at execute
-system.cpu.iew.exec_branches 233410057 # Number of branches executed
-system.cpu.iew.exec_nop 371 # number of nop insts executed
-system.cpu.iew.exec_rate 1.517006 # Inst execution rate
-system.cpu.iew.exec_refs 747857641 # number of memory reference insts executed
-system.cpu.iew.exec_stores 187754946 # Number of stores executed
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.iewBlockCycles 24201668 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 626078428 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 573 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 5945884 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 225252424 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2211114719 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 560102695 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21129397 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1950537549 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1433857 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread0.forwLoads 54506765 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.memOrderViolation 734835 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.squashedLoads 140151655 # Number of loads squashed
-system.cpu.iew.lsq.thread0.squashedStores 50405377 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.wb_consumers 2256424150 # num instructions consuming a value
-system.cpu.iew.wb_count 1928710637 # cumulative count of insts written-back
-system.cpu.iew.wb_fanout 0.551017 # average fanout of values written-back
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.wb_producers 1243327288 # num instructions producing a value
-system.cpu.iew.wb_rate 1.500030 # insts written-back per cycle
-system.cpu.iew.wb_sent 1934940770 # cumulative count of insts sent to commit
-system.cpu.int_regfile_reads 5040549881 # number of integer regfile reads
-system.cpu.int_regfile_writes 1533135927 # number of integer regfile writes
-system.cpu.ipc 1.340099 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.340099 # IPC: Total IPC of All Threads
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1212590834 61.50% 61.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1140241 0.06% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 568540639 28.84% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 189395216 9.61% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1971666946 # Type of FU issued
-system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 120 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 51 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 94 # Number of floating instruction queue writes
-system.cpu.iq.fu_busy_cnt 20875026 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010588 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 491210 2.35% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19087912 91.44% 93.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1295902 6.21% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.int_alu_accesses 1992541909 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 5201971393 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 1928710586 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 2696699928 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 2211113711 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1971666946 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 637 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 484979968 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 663629 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 843902514 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.issued_per_cycle::samples 1237098966 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.593783 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.635374 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 418606363 33.84% 33.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 277983689 22.47% 56.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 220653980 17.84% 74.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 149807025 12.11% 86.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 89527255 7.24% 93.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 51723580 4.18% 97.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 17902939 1.45% 99.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 8343412 0.67% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2550723 0.21% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1237098966 # Number of insts issued each cycle
-system.cpu.iq.rate 1.533439 # Inst issue rate
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 1892006 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34501.539320 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31341.195670 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 979915 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 31468543500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 912091 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 28586022500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 912091 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7649997 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34318.289104 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.516872 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5630330 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 69311516000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.264009 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2019667 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency 62868927000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264008 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2019657 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 3122149 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 3122149 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3935.335196 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.653954 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 3580 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 14088500 # number of cycles access was blocked
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9570827 # number of replacements
+system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use
+system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 666909088 # number of overall hits
+system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 15639225 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 3128328 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 2927819 # number of replacements
+system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 6635428 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 2940239 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9542003 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34375.299564 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6610245 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 100780059500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.307248 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2931758 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 91454949500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.307247 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2931748 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 15990.396178 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 10810.627507 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.487988 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.329914 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 9542003 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34375.299564 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.683001 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 6610245 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 100780059500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.307248 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2931758 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 91454949500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.307247 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2931748 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 1217598 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2919341 # number of replacements
-system.cpu.l2cache.sampled_refs 2946667 # Sample count of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 26801.023686 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7820318 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 143319905000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1216305 # number of writebacks
-system.cpu.memDep0.conflictingLoads 95681801 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 90040335 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 626078428 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 225252424 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 2884001507 # number of misc regfile reads
-system.cpu.misc_regfile_writes 128 # number of misc regfile writes
-system.cpu.numCycles 1285781107 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.BlockCycles 67172415 # Number of cycles rename is blocking
-system.cpu.rename.CommittedMaps 1360917377 # Number of HB maps that are committed
-system.cpu.rename.IQFullEvents 14851346 # Number of times rename has blocked due to IQ full
-system.cpu.rename.IdleCycles 600335413 # Number of cycles rename is idle
-system.cpu.rename.LSQFullEvents 40774846 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.ROBFullEvents 10242 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RenameLookups 6331353991 # Number of register rename lookups that rename has made
-system.cpu.rename.RenamedInsts 2292668273 # Number of instructions processed by rename
-system.cpu.rename.RenamedOperands 1803116545 # Number of destination operands rename has renamed
-system.cpu.rename.RunCycles 438383597 # Number of cycles rename is running
-system.cpu.rename.SquashCycles 70439042 # Number of cycles rename is squashing
-system.cpu.rename.UnblockCycles 60752889 # Number of cycles rename is unblocking
-system.cpu.rename.UndoneMaps 442199165 # Number of HB maps that are undone due to squashing
-system.cpu.rename.fp_rename_lookups 393 # Number of floating rename lookups
-system.cpu.rename.int_rename_lookups 6331353598 # Number of integer rename lookups
-system.cpu.rename.serializeStallCycles 15610 # count of cycles rename stalled for serializing inst
-system.cpu.rename.serializingInsts 650 # count of serializing insts renamed
-system.cpu.rename.skidInsts 118137729 # count of insts added to the skid buffer
-system.cpu.rename.tempSerializingInsts 645 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 3320275044 # The number of ROB reads
-system.cpu.rob.rob_writes 4492885352 # The number of ROB writes
-system.cpu.timesIdled 1544733 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.num_syscalls 46 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff