CPU: Update stats now that there's no fetch in the middle of macroops.

[gem5.git] / tests / long / 70.twolf / ref / sparc / linux / simple-timing / stats.txt

diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 571ff6af88ce2cb5e51c494a598b1a7891174380..f73a0dcbf7fa154318113306f01969322096c771 100644 (file)
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1319897                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 209760                       # Number of bytes of host memory used
-host_seconds                                   146.56                       # Real time elapsed on the host
-host_tick_rate                             1846186883                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 732316                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209324                       # Number of bytes of host memory used
+host_seconds                                   264.15                       # Real time elapsed on the host
+host_tick_rate                             1024317022                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   193444769                       # Number of instructions simulated
-sim_seconds                                  0.270579                       # Number of seconds simulated
-sim_ticks                                270578573000                       # Number of ticks simulated
+sim_seconds                                  0.270578                       # Number of seconds simulated
+sim_ticks                                270578335000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           57735069                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
@@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                      2                       # number of replacements
 system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1237.193452                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1237.193190                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 76732338                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        2                       # number of writebacks
-system.cpu.icache.ReadReq_accesses          193445787                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses          193445549                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 26294.433594                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              193433499                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits              193433261                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency      323106000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000064                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                12288                       # number of ReadReq misses
@@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000064                       # ms
 system.cpu.icache.ReadReq_mshr_misses           12288                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               15741.658447                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               15741.639079                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           193445787                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses           193445549                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 26294.433594                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               193433499                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits               193433261                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency       323106000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000064                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 12288                       # number of demand (read+write) misses
@@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses            12288                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses          193445787                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              193433499                       # number of overall hits
+system.cpu.icache.overall_hits              193433261                       # number of overall hits
 system.cpu.icache.overall_miss_latency      323106000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000064                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                12288                       # number of overall misses
@@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  10362                       # number of replacements
 system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1591.566927                       # Cycle average of tags in use
-system.cpu.icache.total_refs                193433499                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1591.566647                       # Cycle average of tags in use
+system.cpu.icache.total_refs                193433261                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  4072                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2657.329033                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2657.327979                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    8691                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        541157146                       # number of cpu cycles simulated
+system.cpu.numCycles                        541156670                       # number of cpu cycles simulated
 system.cpu.num_insts                        193444769                       # Number of instructions executed
 system.cpu.num_refs                          76733959                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             401                       # Number of system calls