arch: Fix VecReg container alignement to 128bits view

[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-o3 / config.ini

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 6d056728418deab84d6e0a52df4efe1457c83def..c48ceb21fbca7b417a9ce31833182f77d740a6f1 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -12,40 +12,48 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+default_p_state=UNDEFINED
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
+exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
-have_generic_timer=false
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+mem_ranges=2147483648:2415919103:0:0:0:0
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
 multi_proc=true
+multi_thread=false
 num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+power_model=Null
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -58,9 +66,14 @@ system_port=system.membus.slave[1]
 [system.bridge]
 type=Bridge
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 delay=50000
 eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -86,7 +99,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -109,7 +122,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
 checker=Null
 clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
@@ -121,6 +134,7 @@ cpu_id=0
 decodeToFetchDelay=1
 decodeToRenameDelay=2
 decodeWidth=3
+default_p_state=UNDEFINED
 dispatchWidth=6
 do_checkpoint_insts=true
 do_quiesce=true
@@ -159,6 +173,10 @@ numPhysIntRegs=128
 numROBEntries=40
 numRobs=1
 numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -180,6 +198,7 @@ socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
+syscallRetryLatency=10000
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -189,7 +208,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
 BTBEntries=2048
 BTBTagSize=18
 RASSize=16
@@ -198,35 +217,45 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
 numThreads=1
-predType=bi-mode
+useIndirect=true
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -235,16 +264,23 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -258,11 +294,15 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
 [system.cpu.dstage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -275,9 +315,14 @@ walker=system.cpu.dtb.walker
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -297,9 +342,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -311,263 +356,298 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
 
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
 
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
 count=2
 eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
 
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -576,10 +656,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -587,6 +673,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -597,8 +684,6 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
@@ -609,8 +694,6 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
 midr=1091551472
 pmu=Null
 system=system
@@ -620,6 +703,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -633,11 +717,15 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
 [system.cpu.istage2_mmu.stage2_tlb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -650,34 +738,46 @@ walker=system.cpu.itb.walker
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=20
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
 sequential_access=false
 size=4194304
 system=system
+tag_latency=20
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
@@ -686,22 +786,45 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=4194304
+tag_latency=20
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -731,37 +854,50 @@ sys=system
 [system.iobus]
 type=NoncoherentXBar
 clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=true
-width=8
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+response_latency=2
+use_default_range=false
+width=16
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
-type=BaseCache
+type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
+data_latency=50
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
 sequential_access=false
 size=1024
 system=system
+tag_latency=50
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[27]
+writeback_clean=false
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -769,33 +905,53 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+data_latency=50
+default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=50
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
 sequential_access=false
 size=1024
+tag_latency=50
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=0
 pio_latency=100000
 pio_size=8
+power_model=Null
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -806,40 +962,48 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
 clk_domain=system.clk_domain
 conf_table_reported=true
+default_p_state=UNDEFINED
 device_bus_width=8
 device_rowbuffer_size=1024
 device_size=536870912
@@ -847,12 +1011,17 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
 null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 page_policy=open_adaptive
-range=2147483648:2415919103
+power_model=Null
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -874,9 +1043,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -885,22 +1054,24 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470024192
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[18]
 
@@ -981,42 +1152,128 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
+default_p_state=UNDEFINED
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
+power_model=Null
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
 int_num=46
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=471793664
 pio_latency=10000
 pixel_clock=41667
+power_model=Null
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
+
+[system.realview.dcc]
+type=SubSystem
+children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
+eventq_index=0
+thermal_domain=Null
+
+[system.realview.dcc.osc_cpu]
+type=RealViewOsc
+dcc=0
+device=0
+eventq_index=0
+freq=16667
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
+
+[system.realview.dcc.osc_ddr]
+type=RealViewOsc
+dcc=0
+device=8
+eventq_index=0
+freq=25000
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
+
+[system.realview.dcc.osc_hsbm]
+type=RealViewOsc
+dcc=0
+device=4
+eventq_index=0
+freq=25000
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
+
+[system.realview.dcc.osc_pxl]
+type=RealViewOsc
+dcc=0
+device=5
+eventq_index=0
+freq=42105
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
+
+[system.realview.dcc.osc_smb]
+type=RealViewOsc
+dcc=0
+device=6
+eventq_index=0
+freq=20000
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
+
+[system.realview.dcc.osc_sys]
+type=RealViewOsc
+dcc=0
+device=7
+eventq_index=0
+freq=16667
+parent=system.realview.realview_io
+position=0
+site=1
+voltage_domain=system.voltage_domain
 
 [system.realview.energy_ctrl]
 type=EnergyCtrl
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 dvfs_handler=system.dvfs_handler
 eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470286336
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[22]
 
@@ -1096,17 +1353,22 @@ SubsystemVendorID=32902
 VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
+default_p_state=UNDEFINED
 eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
+power_model=Null
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1116,15 +1378,15 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
 eventq_index=0
 gic=system.realview.gic
-int_num=29
+int_phys=29
+int_virt=27
 system=system
 
 [system.realview.gic]
@@ -1132,13 +1394,18 @@ type=Pl390
 clk_domain=system.clk_domain
 cpu_addr=738205696
 cpu_pio_delay=10000
+default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=false
 int_latency=10000
 it_lines=128
-msix_addr=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 platform=system.realview
+power_model=Null
 system=system
 pio=system.membus.master[2]
 
@@ -1146,17 +1413,26 @@ pio=system.membus.master[2]
 type=HDLcd
 amba_id=1314816
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 enable_capture=true
 eventq_index=0
 gic=system.realview.gic
 int_num=117
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=721420288
 pio_latency=10000
-pixel_clock=7299
+pixel_buffer_size=2048
+pixel_chunk=32
+power_model=Null
+pxl_clk=system.realview.dcc.osc_pxl
 system=system
 vnc=system.vncserver
+workaround_dma_line_count=true
+workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1235,16 +1511,20 @@ VendorID=32902
 clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
+default_p_state=UNDEFINED
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
+power_model=Null
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1252,40 +1532,55 @@ pio=system.iobus.master[23]
 type=Pl050
 amba_id=1314896
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
 int_num=44
 is_mouse=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470155264
 pio_latency=100000
+power_model=Null
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_delay=1000000
 int_num=45
 is_mouse=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470220800
 pio_latency=100000
+power_model=Null
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=739246080
 pio_latency=100000
 pio_size=4095
+power_model=Null
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1299,11 +1594,16 @@ pio=system.iobus.master[12]
 [system.realview.lan_fake]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=436207616
 pio_latency=100000
 pio_size=65535
+power_model=Null
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1317,23 +1617,93 @@ pio=system.iobus.master[19]
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=738721792
 pio_latency=100000
+power_model=Null
+system=system
+pio=system.membus.master[4]
+
+[system.realview.mcc]
+type=SubSystem
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
+eventq_index=0
+thermal_domain=Null
+
+[system.realview.mcc.osc_clcd]
+type=RealViewOsc
+dcc=0
+device=1
+eventq_index=0
+freq=42105
+parent=system.realview.realview_io
+position=0
+site=0
+voltage_domain=system.voltage_domain
+
+[system.realview.mcc.osc_mcc]
+type=RealViewOsc
+dcc=0
+device=0
+eventq_index=0
+freq=20000
+parent=system.realview.realview_io
+position=0
+site=0
+voltage_domain=system.voltage_domain
+
+[system.realview.mcc.osc_peripheral]
+type=RealViewOsc
+dcc=0
+device=2
+eventq_index=0
+freq=41667
+parent=system.realview.realview_io
+position=0
+site=0
+voltage_domain=system.voltage_domain
+
+[system.realview.mcc.osc_system_bus]
+type=RealViewOsc
+dcc=0
+device=4
+eventq_index=0
+freq=41667
+parent=system.realview.realview_io
+position=0
+site=0
+voltage_domain=system.voltage_domain
+
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
 system=system
-pio=system.membus.master[3]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470089728
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[21]
 
@@ -1342,33 +1712,51 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=false
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:67108863
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
+power_model=Null
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 idreg=35979264
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=469827584
 pio_latency=100000
+power_model=Null
 proc_id0=335544320
 proc_id1=335544320
 system=system
@@ -1378,12 +1766,17 @@ pio=system.iobus.master[1]
 type=PL031
 amba_id=3412017
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
 int_num=36
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=471269376
 pio_latency=100000
+power_model=Null
 system=system
 time=Thu Jan  1 00:00:00 2009
 pio=system.iobus.master[10]
@@ -1392,10 +1785,15 @@ pio=system.iobus.master[10]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=469893120
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[16]
 
@@ -1405,14 +1803,19 @@ amba_id=1316868
 clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_num0=34
 int_num1=34
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470876160
 pio_latency=100000
+power_model=Null
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1420,26 +1823,36 @@ amba_id=1316868
 clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 int_num0=35
 int_num1=35
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470941696
 pio_latency=100000
+power_model=Null
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 end_on_eot=false
 eventq_index=0
 gic=system.realview.gic
 int_delay=100000
 int_num=37
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470351872
 pio_latency=100000
 platform=system.realview
+power_model=Null
 system=system
 terminal=system.terminal
 pio=system.iobus.master[0]
@@ -1448,10 +1861,15 @@ pio=system.iobus.master[0]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470417408
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[13]
 
@@ -1459,10 +1877,15 @@ pio=system.iobus.master[13]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470482944
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[14]
 
@@ -1470,21 +1893,31 @@ pio=system.iobus.master[14]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470548480
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[15]
 
 [system.realview.usb_fake]
 type=IsaFake
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=452984832
 pio_latency=100000
 pio_size=131071
+power_model=Null
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1498,37 +1931,53 @@ pio=system.iobus.master[20]
 [system.realview.vgic]
 type=VGic
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 gic=system.realview.gic
 hv_addr=738213888
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_delay=10000
 platform=system.realview
+power_model=Null
 ppint=25
 system=system
 vcpu_addr=738222080
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.vram]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=false
+default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
-range=402653184:436207615
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
 clk_domain=system.clk_domain
+default_p_state=UNDEFINED
 eventq_index=0
 ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
 pio_addr=470745088
 pio_latency=100000
+power_model=Null
 system=system
 pio=system.iobus.master[17]