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arch: Fix VecReg container alignement to 128bits view
[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-o3 / config.ini
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index c0b6f00cc75bf1ffdd3ce66df383e46537a47fa1..c48ceb21fbca7b417a9ce31833182f77d740a6f1 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
 power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
 reset_addr_64=0
 symbolfile=
 thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -122,7 +122,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
 checker=Null
 clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
@@ -198,6 +198,7 @@ socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
+syscallRetryLatency=10000
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -233,10 +234,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -250,6 +251,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -262,15 +264,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
@@ -373,38 +376,52 @@ pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
 
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=2
 pipelined=true
 
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
 [system.cpu.fuPool.FUList3]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
 
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=2
 pipelined=true
 
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
 [system.cpu.fuPool.FUList4]
 type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
 count=2
 eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
 
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
@@ -536,7 +553,7 @@ pipelined=true
 type=OpDesc
 eventq_index=0
 opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
 pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
@@ -588,6 +605,20 @@ opClass=FloatMult
 opLat=4
 pipelined=true
 
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
 [system.cpu.icache]
 type=Cache
 children=tags
@@ -595,10 +626,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -612,6 +643,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -624,15 +656,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -651,8 +684,6 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
@@ -663,8 +694,6 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
 midr=1091551472
 pmu=Null
 system=system
@@ -727,10 +756,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -744,6 +773,7 @@ response_latency=20
 sequential_access=false
 size=4194304
 system=system
+tag_latency=20
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -756,15 +786,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=4194304
+tag_latency=20
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
@@ -844,10 +875,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+data_latency=50
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=50
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -861,6 +892,7 @@ response_latency=50
 sequential_access=false
 size=1024
 system=system
+tag_latency=50
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -873,15 +905,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+data_latency=50
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=50
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=1024
+tag_latency=50
 
 [system.membus]
 type=CoherentXBar