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arch: Fix VecReg container alignement to 128bits view
[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-o3 / config.ini
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index d075489301fe3f64a9380d4d789f21ceea4f3688..c48ceb21fbca7b417a9ce31833182f77d740a6f1 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,13 +30,13 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
-mem_ranges=2147483648:2415919103
+mem_ranges=2147483648:2415919103:0:0:0:0
 memories=system.physmem system.realview.nvmem system.realview.vram
 mmap_using_noreserve=false
 multi_proc=true
@@ -49,7 +49,7 @@ panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
 power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh
 reset_addr_64=0
 symbolfile=
 thermal_components=
@@ -73,7 +73,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -99,7 +99,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -122,7 +122,7 @@ SSITSize=1024
 activity=0
 backComSize=5
 branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
 checker=Null
 clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
@@ -198,6 +198,7 @@ socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
+syscallRetryLatency=10000
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
@@ -229,14 +230,14 @@ useIndirect=true
 [system.cpu.dcache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=4
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=4
@@ -250,6 +251,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -262,15 +264,16 @@ type=LRU
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.dstage2_mmu]
 type=ArmStage2MMU
@@ -373,38 +376,52 @@ pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
 
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemRead
 opLat=2
 pipelined=true
 
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
 [system.cpu.fuPool.FUList3]
 type=FUDesc
-children=opList
+children=opList0 opList1
 count=1
 eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
 
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
 opClass=MemWrite
 opLat=2
 pipelined=true
 
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
 [system.cpu.fuPool.FUList4]
 type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
 count=2
 eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
 
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
@@ -536,7 +553,7 @@ pipelined=true
 type=OpDesc
 eventq_index=0
 opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
 pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
@@ -588,17 +605,31 @@ opClass=FloatMult
 opLat=4
 pipelined=true
 
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
 [system.cpu.icache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=1
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=true
 max_miss_count=0
 mshrs=4
@@ -612,6 +643,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
@@ -624,15 +656,16 @@ type=LRU
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -651,8 +684,6 @@ id_aa64isar0_el1=0
 id_aa64isar1_el1=0
 id_aa64mmfr0_el1=15728642
 id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
@@ -663,8 +694,6 @@ id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
 id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
 midr=1091551472
 pmu=Null
 system=system
@@ -723,14 +752,14 @@ port=system.cpu.toL2Bus.slave[2]
 [system.cpu.l2cache]
 type=Cache
 children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -744,6 +773,7 @@ response_latency=20
 sequential_access=false
 size=4194304
 system=system
+tag_latency=20
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -756,15 +786,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=4194304
+tag_latency=20
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
@@ -840,14 +871,14 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 [system.iocache]
 type=Cache
 children=tags
-addr_ranges=2147483648:2415919103
+addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+data_latency=50
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=50
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -861,6 +892,7 @@ response_latency=50
 sequential_access=false
 size=1024
 system=system
+tag_latency=50
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -873,19 +905,20 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+data_latency=50
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=50
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=1024
+tag_latency=50
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
 eventq_index=0
@@ -897,7 +930,7 @@ p_state_clk_gate_min=1000
 point_of_coherency=true
 power_model=Null
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -929,29 +962,36 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
 IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
 IDD2N2=0.000000
 IDD2P0=0.000000
 IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
 IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
 IDD3N2=0.000000
 IDD3P0=0.000000
 IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
 IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
 IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
 IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
 IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
 IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
@@ -971,6 +1011,7 @@ devices_per_rank=8
 dll=true
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 max_accesses_per_row=16
 mem_sched_policy=frfcfs
 min_writes_per_switch=16
@@ -980,7 +1021,7 @@ p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 page_policy=open_adaptive
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
@@ -1002,9 +1043,9 @@ tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
-tXP=0
+tXP=6000
 tXPDLL=0
-tXS=0
+tXS=270000
 tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
@@ -1357,7 +1398,7 @@ default_p_state=UNDEFINED
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
-gem5_extensions=true
+gem5_extensions=false
 int_latency=10000
 it_lines=128
 p_state_clk_gate_bins=20
@@ -1674,6 +1715,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1681,7 +1723,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=0:67108863
+range=0:67108863:0:0:0:0
 port=system.membus.master[1]
 
 [system.realview.pci_host]
@@ -1912,6 +1954,7 @@ conf_table_reported=false
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=30000
 latency_var=0
 null=false
@@ -1919,7 +1962,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
-range=402653184:436207615
+range=402653184:436207615:0:0:0:0
 port=system.iobus.master[11]
 
 [system.realview.watchdog_fake]