---------- Begin Simulation Statistics ----------
sim_seconds 2.832863 # Number of seconds simulated
-sim_ticks 2832863135500 # Number of ticks simulated
-final_tick 2832863135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2832862976500 # Number of ticks simulated
+final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115587 # Simulator instruction rate (inst/s)
-host_op_rate 140197 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2895087258 # Simulator tick rate (ticks/s)
-host_mem_usage 586016 # Number of bytes of host memory used
-host_seconds 978.51 # Real time elapsed on the host
-sim_insts 113102806 # Number of instructions simulated
-sim_ops 137183832 # Number of ops (including micro ops) simulated
+host_inst_rate 118929 # Simulator instruction rate (inst/s)
+host_op_rate 144250 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2978848657 # Simulator tick rate (ticks/s)
+host_mem_usage 586012 # Number of bytes of host memory used
+host_seconds 950.99 # Real time elapsed on the host
+sim_insts 113100501 # Number of instructions simulated
+sim_ops 137180951 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1320448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9385192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10708200 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1320448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1320448 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8027392 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8044916 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22879 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147164 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170083 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 125428 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129809 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 466118 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3312971 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3779992 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 466118 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 466118 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2833667 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2839853 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2833667 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 466118 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3319156 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6619845 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170084 # Number of read requests accepted
-system.physmem.writeReqs 129809 # Number of write requests accepted
-system.physmem.readBursts 170084 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129809 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10877056 # Total number of bytes read from DRAM
+system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170065 # Number of read requests accepted
+system.physmem.writeReqs 129793 # Number of write requests accepted
+system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8057984 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10708264 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8044916 # Total written bytes from the system interface side
+system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11273 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10590 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10987 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11172 # Per bank write bursts
-system.physmem.perBankRdBursts::4 12956 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9956 # Per bank write bursts
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-system.physmem.perBankRdBursts::7 10745 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10596 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10173 # Per bank write bursts
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+system.physmem.perBankRdBursts::8 10600 # Per bank write bursts
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system.physmem.perBankRdBursts::10 10343 # Per bank write bursts
system.physmem.perBankRdBursts::11 9301 # Per bank write bursts
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-system.physmem.perBankRdBursts::14 10190 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10133 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8501 # Per bank write bursts
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-system.physmem.perBankWrBursts::2 8565 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8669 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7365 # Per bank write bursts
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-system.physmem.perBankWrBursts::7 8000 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7673 # Per bank write bursts
system.physmem.perBankWrBursts::10 7751 # Per bank write bursts
system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
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-system.physmem.perBankWrBursts::13 8385 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7646 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7482 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7477 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
-system.physmem.totGap 2832862903500 # Total gap between requests
+system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
+system.physmem.totGap 2832862744500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166532 # Read request sizes (log2)
+system.physmem.readPktSize::6 166513 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 125428 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::58 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 61981 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 305.496459 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.645422 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.944153 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23140 37.33% 37.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14875 24.00% 61.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6518 10.52% 71.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3622 5.84% 77.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2531 4.08% 81.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1654 2.67% 84.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1506 2.43% 86.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1111 1.79% 88.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7024 11.33% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61981 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6159 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.593765 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 568.835471 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6158 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6159 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6159 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.442604 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.500292 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.099847 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5468 88.78% 88.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 102 1.66% 90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 31 0.50% 90.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 55 0.89% 91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 28 0.45% 92.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 20 0.32% 92.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 47 0.76% 93.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 12 0.19% 93.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 146 2.37% 95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 14 0.23% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 5 0.08% 96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 12 0.19% 96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 62 1.01% 97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.10% 97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 7 0.11% 97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 23 0.37% 98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 90 1.46% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.05% 99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.02% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.02% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 3 0.05% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 5 0.08% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6159 # Writes before turning the bus around for reads
-system.physmem.totQLat 2118470000 # Total ticks spent queuing
-system.physmem.totMemAccLat 5305107500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849770000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12464.96 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads
+system.physmem.totQLat 2126742000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31214.96 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 139692 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94186 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
-system.physmem.avgGap 9446245.51 # Average gap between requests
-system.physmem.pageHitRate 79.05 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 242388720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 132255750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 687663600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 417033360 # Energy for write commands per rank (pJ)
+system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
+system.physmem.readRowHits 139707 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94201 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes
+system.physmem.avgGap 9447347.56 # Average gap between requests
+system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83434510665 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626525439500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1896467659275 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.454308 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705731371250 # Time in different power states
+system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.453835 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states
system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32529373750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 226187640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 637969800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 398837520 # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82104234975 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1627692348000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1896211361490 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.363834 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2707689162500 # Time in different power states
+system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.365771 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states
system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30578679500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46808005 # Number of BP lookups
-system.cpu.branchPred.condPredicted 23978413 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1175283 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29454237 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13525326 # Number of BTB hits
+system.cpu.branchPred.lookups 46806016 # Number of BP lookups
+system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 45.919798 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11724965 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 34889 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 7914908 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 7768670 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 146238 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 60204 # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 72355 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 72355 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29395 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23194 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19766 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52589 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 463.728156 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2807.068133 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191 51286 97.52% 97.52% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.24% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575 316 0.60% 99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 72368 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151 23 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52589 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 17730 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8394.043940 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 17507 98.74% 98.74% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535 217 1.22% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 17730 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131327621316 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.619198 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.492781 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 131267451816 99.95% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 41041000 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 8807000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 6837500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 1021000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 576000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 474000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131327621316 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6380 82.61% 82.61% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1343 17.39% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7723 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72355 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72355 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7723 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7723 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 80078 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25411177 # DTB read hits
-system.cpu.dtb.read_misses 62688 # DTB read misses
-system.cpu.dtb.write_hits 19865478 # DTB write hits
-system.cpu.dtb.write_misses 9667 # DTB write misses
+system.cpu.dtb.read_hits 25410889 # DTB read hits
+system.cpu.dtb.read_misses 62740 # DTB read misses
+system.cpu.dtb.write_hits 19865162 # DTB write hits
+system.cpu.dtb.write_misses 9628 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1317 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25473865 # DTB read accesses
-system.cpu.dtb.write_accesses 19875145 # DTB write accesses
+system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25473629 # DTB read accesses
+system.cpu.dtb.write_accesses 19874790 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45276655 # DTB hits
-system.cpu.dtb.misses 72355 # DTB misses
-system.cpu.dtb.accesses 45349010 # DTB accesses
+system.cpu.dtb.hits 45276051 # DTB hits
+system.cpu.dtb.misses 72368 # DTB misses
+system.cpu.dtb.accesses 45348419 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 12837 # Table walker walks requested
-system.cpu.itb.walker.walksShort 12837 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3369 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7745 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 1723 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11114 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 758.457801 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 3142.171422 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.66% 94.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 120 1.08% 95.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 234 2.11% 97.85% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 132 1.19% 99.04% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 45 0.40% 99.44% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 12817 # Table walker walks requested
+system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11114 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 5038 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12015.680826 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 9674.005789 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7624.491394 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 4083 81.04% 81.04% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 936 18.58% 99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 5038 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 23953376916 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.632532 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.482296 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 8804085500 36.76% 36.76% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 15147384416 63.24% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 1819000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 23953376916 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12837 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 12837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 16152 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 65992511 # ITB inst hits
-system.cpu.itb.inst_misses 12837 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 65995629 # ITB inst hits
+system.cpu.itb.inst_misses 12817 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3079 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2160 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66005348 # ITB inst accesses
-system.cpu.itb.hits 65992511 # DTB hits
-system.cpu.itb.misses 12837 # DTB misses
-system.cpu.itb.accesses 66005348 # DTB accesses
-system.cpu.numCycles 278422079 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66008446 # ITB inst accesses
+system.cpu.itb.hits 65995629 # DTB hits
+system.cpu.itb.misses 12817 # DTB misses
+system.cpu.itb.accesses 66008446 # DTB accesses
+system.cpu.numCycles 278423951 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104965644 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184047232 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46808005 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33018961 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 161470061 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6057656 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 190492 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 8321 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 345001 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 554797 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 65991288 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1042618 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6254 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 270563337 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.829471 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.217030 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 171642539 63.44% 63.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29152189 10.77% 74.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14033587 5.19% 79.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55735022 20.60% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 270563337 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.168119 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.661037 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 77947938 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 121878006 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64302075 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3866348 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2568970 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3407378 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 156978056 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3511118 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2568970 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83705242 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11815574 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76555831 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62411209 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33506511 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146428655 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 918489 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 467718 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 65503 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 18531 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 30749318 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150222579 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 676982359 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 163959933 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 10887 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141740582 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8481991 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2839527 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2643996 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13883864 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26339284 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21214862 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1704584 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2138851 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143220356 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2117775 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143040703 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 261102 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8154295 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14292577 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 121903 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 270563337 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.528677 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.865235 # Number of insts issued each cycle
+system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 676972712 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 182376042 67.41% 67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45230245 16.72% 84.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31877858 11.78% 95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10262059 3.79% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 817100 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 270563337 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7341205 32.76% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5622623 25.09% 57.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9446888 42.15% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95846012 67.01% 67.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 114315 0.08% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8579 0.01% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26129650 18.27% 85.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 20939810 14.64% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143040703 # Type of FU issued
-system.cpu.iq.rate 0.513755 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22410748 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156674 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 579280960 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 153497939 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 139990284 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35633 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165425721 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23393 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 323902 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued
+system.cpu.iq.rate 0.513744 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1435157 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 717 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18681 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 624055 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 88621 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6303 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2568970 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1238473 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 546153 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145518660 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26339284 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21214862 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1094251 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17896 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 509714 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18681 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 277446 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471378 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 748824 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142140939 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25734314 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 827514 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 180529 # number of nop insts executed
-system.cpu.iew.exec_refs 46562087 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26490837 # Number of branches executed
-system.cpu.iew.exec_stores 20827773 # Number of stores executed
-system.cpu.iew.exec_rate 0.510523 # Inst execution rate
-system.cpu.iew.wb_sent 141772110 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140001653 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63237844 # num instructions producing a value
-system.cpu.iew.wb_consumers 95709593 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.502840 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660726 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7370888 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995872 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 715425 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 267671554 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.513087 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.118264 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 180634 # number of nop insts executed
+system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26490215 # Number of branches executed
+system.cpu.iew.exec_stores 20827406 # Number of stores executed
+system.cpu.iew.exec_rate 0.510511 # Inst execution rate
+system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63237138 # num instructions producing a value
+system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 194234773 72.56% 72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43288369 16.17% 88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15457266 5.77% 94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4372596 1.63% 96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6412647 2.40% 98.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1623966 0.61% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 797879 0.30% 99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 412108 0.15% 99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1071950 0.40% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 267671554 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113257711 # Number of instructions committed
-system.cpu.commit.committedOps 137338737 # Number of ops (including micro ops) committed
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+system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu.commit.loads 24904127 # Number of loads committed
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system.cpu.commit.membars 814876 # Number of memory barriers committed
-system.cpu.commit.branches 26024432 # Number of branches committed
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-system.cpu.commit.int_insts 120166310 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4884393 # Number of function calls committed.
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system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24904127 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20590807 14.99% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137338737 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1071950 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 389122780 # The number of ROB reads
-system.cpu.rob.rob_writes 292297911 # The number of ROB writes
-system.cpu.timesIdled 890833 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7858742 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5387304193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113102806 # Number of Instructions Simulated
-system.cpu.committedOps 137183832 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.461673 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.461673 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.406228 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.406228 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155527774 # number of integer regfile reads
-system.cpu.int_regfile_writes 88490353 # number of integer regfile writes
-system.cpu.fp_regfile_reads 9528 # number of floating regfile reads
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+system.cpu.rob.rob_reads 389119867 # The number of ROB reads
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+system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads
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system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
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-system.cpu.dcache.tags.sampled_refs 839336 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 47.724947 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 16632.119452 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 64437.357433 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13773.679018 # average LoadLockedReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 54384.889903 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 869086 # number of cycles access was blocked
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+system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6864 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.615093 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 696811 # number of writebacks
-system.cpu.dcache.writebacks::total 696811 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290488 # number of ReadReq MSHR hits
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193343.290374 # average overall mshr uncacheable latency
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-system.cpu.l2cache.demand_mshr_miss_latency::total 20341710003 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17907785500 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 736000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2434936503 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17903595500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 20341710003 # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17907785500 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887116000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227183500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756897000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756897000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887147000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227214500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644013000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984080500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887147000 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.979437 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.979437 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.977706 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.977706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010540 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024422 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024422 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455857 # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024401 # mshr miss rate for ReadSharedReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.060318 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060313 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.060318 # mshr miss rate for overall accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127120 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127100 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196 # average ReadSharedReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277 # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5483816 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2557705 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 822252 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1886159 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 149793 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2777 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 297269 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 297269 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886711 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 542312 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665508 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640654 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30972 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133892 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8471026 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241506672 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98506345 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48452 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232436 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340293905 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 194298 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3054873 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.024677 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.155138 # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 194360 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2979489 97.53% 97.53% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 75384 2.47% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3054873 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5401857499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2834033066 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1305567557 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 18867982 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 75841383 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43093000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6154500 # Layer occupancy (ticks)
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system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33075500 # Layer occupancy (ticks)
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-system.iobus.reqLayer25.occupancy 187134993 # Layer occupancy (ticks)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
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system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
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system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
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system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126259.538117 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865 # average WriteLineReq miss latency
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-system.iocache.demand_avg_miss_latency::total 126259.538117 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126259.538117 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126259.538117 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
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+system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
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system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
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-system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.membus.trans_dist::ReadReq 34132 # Transaction distribution
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system.membus.trans_dist::WriteReq 27585 # Transaction distribution
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-system.membus.trans_dist::WritebackDirty 125428 # Transaction distribution
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system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
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system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18916505 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 487 # Total snoops (count)
-system.membus.snoop_fanout::samples 402766 # Request fanout histogram
+system.membus.snoop_fanout::samples 402739 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402766 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
projects / gem5.git / blobdiff