---------- Begin Simulation Statistics ----------
-sim_seconds 2.502550 # Number of seconds simulated
-sim_ticks 2502549875500 # Number of ticks simulated
-final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.526147 # Number of seconds simulated
+sim_ticks 2526146947500 # Number of ticks simulated
+final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75474 # Simulator instruction rate (inst/s)
-host_op_rate 97450 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3170228022 # Simulator tick rate (ticks/s)
-host_mem_usage 386888 # Number of bytes of host memory used
-host_seconds 789.39 # Real time elapsed on the host
-sim_insts 59578267 # Number of instructions simulated
-sim_ops 76925839 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory
-system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory
+host_inst_rate 57077 # Simulator instruction rate (inst/s)
+host_op_rate 73443 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2390895648 # Simulator tick rate (ticks/s)
+host_mem_usage 424332 # Number of bytes of host memory used
+host_seconds 1056.57 # Real time elapsed on the host
+sim_insts 60306154 # Number of instructions simulated
+sim_ops 77597242 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096836 # Number of read requests accepted
+system.physmem.writeReqs 813120 # Number of write requests accepted
+system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 943582 # Per bank write bursts
+system.physmem.perBankRdBursts::1 943071 # Per bank write bursts
+system.physmem.perBankRdBursts::2 939289 # Per bank write bursts
+system.physmem.perBankRdBursts::3 939279 # Per bank write bursts
+system.physmem.perBankRdBursts::4 943119 # Per bank write bursts
+system.physmem.perBankRdBursts::5 943242 # Per bank write bursts
+system.physmem.perBankRdBursts::6 939090 # Per bank write bursts
+system.physmem.perBankRdBursts::7 938633 # Per bank write bursts
+system.physmem.perBankRdBursts::8 943981 # Per bank write bursts
+system.physmem.perBankRdBursts::9 943506 # Per bank write bursts
+system.physmem.perBankRdBursts::10 938534 # Per bank write bursts
+system.physmem.perBankRdBursts::11 937721 # Per bank write bursts
+system.physmem.perBankRdBursts::12 943933 # Per bank write bursts
+system.physmem.perBankRdBursts::13 943406 # Per bank write bursts
+system.physmem.perBankRdBursts::14 939034 # Per bank write bursts
+system.physmem.perBankRdBursts::15 938886 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6687 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6452 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6617 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6618 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6551 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6799 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6798 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6724 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7121 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6870 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6536 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6184 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7152 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6752 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7039 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6901 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 2526145872500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 38 # Read request sizes (log2)
+system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 154590 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 754018 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 59102 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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-system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54877277 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149448 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149448 # Transaction distribution
+system.membus.trans_dist::WriteReq 763332 # Transaction distribution
+system.membus.trans_dist::WriteResp 763332 # Transaction distribution
+system.membus.trans_dist::Writeback 59102 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131427 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131427 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138628065 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.iobus.throughput 48266379 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121927965 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 14756776 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions.
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15048164 # DTB read hits
-system.cpu.checker.dtb.read_misses 7309 # DTB read misses
-system.cpu.checker.dtb.write_hits 11293826 # DTB write hits
-system.cpu.checker.dtb.write_misses 2190 # DTB write misses
+system.cpu.checker.dtb.read_hits 14986903 # DTB read hits
+system.cpu.checker.dtb.read_misses 7307 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227441 # DTB write hits
+system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994210 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229632 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26341990 # DTB hits
-system.cpu.checker.dtb.misses 9499 # DTB misses
-system.cpu.checker.dtb.accesses 26351489 # DTB accesses
-system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits
-system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
+system.cpu.checker.dtb.hits 26214344 # DTB hits
+system.cpu.checker.dtb.misses 9498 # DTB misses
+system.cpu.checker.dtb.accesses 26223842 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.inst_hits 61480126 # ITB inst hits
+system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses
-system.cpu.checker.itb.hits 60744881 # DTB hits
-system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 60749352 # DTB accesses
-system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 61484599 # ITB inst accesses
+system.cpu.checker.itb.hits 61480126 # DTB hits
+system.cpu.checker.itb.misses 4473 # DTB misses
+system.cpu.checker.itb.accesses 61484599 # DTB accesses
+system.cpu.checker.numCycles 77883033 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51771660 # DTB read hits
-system.cpu.dtb.read_misses 81258 # DTB read misses
-system.cpu.dtb.write_hits 11880398 # DTB write hits
-system.cpu.dtb.write_misses 17961 # DTB write misses
+system.cpu.dtb.read_hits 51181584 # DTB read hits
+system.cpu.dtb.read_misses 65031 # DTB read misses
+system.cpu.dtb.write_hits 11699885 # DTB write hits
+system.cpu.dtb.write_misses 15694 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51852918 # DTB read accesses
-system.cpu.dtb.write_accesses 11898359 # DTB write accesses
+system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51246615 # DTB read accesses
+system.cpu.dtb.write_accesses 11715579 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63652058 # DTB hits
-system.cpu.dtb.misses 99219 # DTB misses
-system.cpu.dtb.accesses 63751277 # DTB accesses
-system.cpu.itb.inst_hits 13142261 # ITB inst hits
-system.cpu.itb.inst_misses 12247 # ITB inst misses
+system.cpu.dtb.hits 62881469 # DTB hits
+system.cpu.dtb.misses 80725 # DTB misses
+system.cpu.dtb.accesses 62962194 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 11524718 # ITB inst hits
+system.cpu.itb.inst_misses 11477 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13154508 # ITB inst accesses
-system.cpu.itb.hits 13142261 # DTB hits
-system.cpu.itb.misses 12247 # DTB misses
-system.cpu.itb.accesses 13154508 # DTB accesses
-system.cpu.numCycles 413642740 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11536195 # ITB inst accesses
+system.cpu.itb.hits 11524718 # DTB hits
+system.cpu.itb.misses 11477 # DTB misses
+system.cpu.itb.accesses 11536195 # DTB accesses
+system.cpu.numCycles 477111575 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued
-system.cpu.iq.rate 0.301258 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued
+system.cpu.iq.rate 0.257621 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 256054 # number of nop insts executed
-system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11412736 # Number of branches executed
-system.cpu.iew.exec_stores 12391364 # Number of stores executed
-system.cpu.iew.exec_rate 0.293583 # Inst execution rate
-system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 46459932 # num instructions producing a value
-system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value
+system.cpu.iew.exec_nop 221300 # number of nop insts executed
+system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11821026 # Number of branches executed
+system.cpu.iew.exec_stores 12211427 # Number of stores executed
+system.cpu.iew.exec_rate 0.253266 # Inst execution rate
+system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47016858 # num instructions producing a value
+system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 59728648 # Number of instructions committed
-system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60456535 # Number of instructions committed
+system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27513345 # Number of memory references committed
-system.cpu.commit.loads 15715170 # Number of loads committed
-system.cpu.commit.membars 413057 # Number of memory barriers committed
-system.cpu.commit.branches 9904308 # Number of branches committed
+system.cpu.commit.refs 27385855 # Number of memory references committed
+system.cpu.commit.loads 15654083 # Number of loads committed
+system.cpu.commit.membars 403571 # Number of memory barriers committed
+system.cpu.commit.branches 10305769 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68616986 # Number of committed integer instructions.
-system.cpu.commit.function_calls 995953 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69188185 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991209 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 246021016 # The number of ROB reads
-system.cpu.rob.rob_writes 206855771 # The number of ROB writes
-system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 59578267 # Number of Instructions Simulated
-system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated
-system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 551124725 # number of integer regfile reads
-system.cpu.int_regfile_writes 87730819 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8186 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2858 # number of floating regfile writes
-system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912697 # number of misc regfile writes
-system.cpu.icache.replacements 991190 # number of replacements
-system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use
-system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits
-system.cpu.icache.overall_hits::total 12061455 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses
-system.cpu.icache.overall_misses::total 1076423 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked
+system.cpu.rob.rob_reads 242914035 # The number of ROB reads
+system.cpu.rob.rob_writes 195975439 # The number of ROB writes
+system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60306154 # Number of Instructions Simulated
+system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated
+system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 548607877 # number of integer regfile reads
+system.cpu.int_regfile_writes 87541392 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8324 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2920 # number of floating regfile writes
+system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.tags.replacements 980909 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits
+system.cpu.icache.overall_hits::total 10459956 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses
+system.cpu.icache.overall_misses::total 1061258 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10015008577 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10015008577 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 140227660304 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 140227660304 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186052000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 186052000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 181002 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks
-system.cpu.dcache.writebacks::total 607543 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks
+system.cpu.dcache.writebacks::total 607582 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs nan # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses 0 # Number of tag accesses
+system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff