---------- Begin Simulation Statistics ----------
-sim_seconds 2.503100 # Number of seconds simulated
-sim_ticks 2503099557500 # Number of ticks simulated
-final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.501686 # Number of seconds simulated
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+final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68083 # Simulator instruction rate (inst/s)
-host_op_rate 87941 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2866621111 # Simulator tick rate (ticks/s)
-host_mem_usage 384248 # Number of bytes of host memory used
-host_seconds 873.19 # Real time elapsed on the host
-sim_insts 59449445 # Number of instructions simulated
-sim_ops 76789092 # Number of ops (including micro ops) simulated
+host_inst_rate 54158 # Simulator instruction rate (inst/s)
+host_op_rate 69928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2274069684 # Simulator tick rate (ticks/s)
+host_mem_usage 384504 # Number of bytes of host memory used
+host_seconds 1100.09 # Real time elapsed on the host
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+system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
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system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s)
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-system.l2c.avg_refs 12.212798 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15016256 # DTB read hits
-system.cpu.checker.dtb.read_misses 7312 # DTB read misses
-system.cpu.checker.dtb.write_hits 11274185 # DTB write hits
-system.cpu.checker.dtb.write_misses 2190 # DTB write misses
+system.cpu.checker.dtb.read_hits 15048343 # DTB read hits
+system.cpu.checker.dtb.read_misses 7305 # DTB read misses
+system.cpu.checker.dtb.write_hits 11293933 # DTB write hits
+system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15023568 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11276375 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15055648 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296124 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26290441 # DTB hits
-system.cpu.checker.dtb.misses 9502 # DTB misses
-system.cpu.checker.dtb.accesses 26299943 # DTB accesses
-system.cpu.checker.itb.inst_hits 60615999 # ITB inst hits
+system.cpu.checker.dtb.hits 26342276 # DTB hits
+system.cpu.checker.dtb.misses 9496 # DTB misses
+system.cpu.checker.dtb.accesses 26351772 # DTB accesses
+system.cpu.checker.itb.inst_hits 60745631 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 60620470 # ITB inst accesses
-system.cpu.checker.itb.hits 60615999 # DTB hits
+system.cpu.checker.itb.inst_accesses 60750102 # ITB inst accesses
+system.cpu.checker.itb.hits 60745631 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 60620470 # DTB accesses
-system.cpu.checker.numCycles 77067453 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 60750102 # DTB accesses
+system.cpu.checker.numCycles 77205204 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51948606 # DTB read hits
-system.cpu.dtb.read_misses 101816 # DTB read misses
-system.cpu.dtb.write_hits 11910706 # DTB write hits
-system.cpu.dtb.write_misses 24423 # DTB write misses
+system.cpu.dtb.read_hits 52103903 # DTB read hits
+system.cpu.dtb.read_misses 93079 # DTB read misses
+system.cpu.dtb.write_hits 11946241 # DTB write hits
+system.cpu.dtb.write_misses 25022 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7999 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 8141 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 52050422 # DTB read accesses
-system.cpu.dtb.write_accesses 11935129 # DTB write accesses
+system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 52196982 # DTB read accesses
+system.cpu.dtb.write_accesses 11971263 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63859312 # DTB hits
-system.cpu.dtb.misses 126239 # DTB misses
-system.cpu.dtb.accesses 63985551 # DTB accesses
-system.cpu.itb.inst_hits 13611127 # ITB inst hits
-system.cpu.itb.inst_misses 11794 # ITB inst misses
+system.cpu.dtb.hits 64050144 # DTB hits
+system.cpu.dtb.misses 118101 # DTB misses
+system.cpu.dtb.accesses 64168245 # DTB accesses
+system.cpu.itb.inst_hits 13717584 # ITB inst hits
+system.cpu.itb.inst_misses 12272 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5224 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5306 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13622921 # ITB inst accesses
-system.cpu.itb.hits 13611127 # DTB hits
-system.cpu.itb.misses 11794 # DTB misses
-system.cpu.itb.accesses 13622921 # DTB accesses
-system.cpu.numCycles 414035717 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
+system.cpu.itb.hits 13717584 # DTB hits
+system.cpu.itb.misses 12272 # DTB misses
+system.cpu.itb.accesses 13729856 # DTB accesses
+system.cpu.numCycles 411352060 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued
-system.cpu.iq.rate 0.303772 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
+system.cpu.iq.rate 0.307159 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 216875 # number of nop insts executed
-system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11533456 # Number of branches executed
-system.cpu.iew.exec_stores 12420416 # Number of stores executed
-system.cpu.iew.exec_rate 0.295954 # Inst execution rate
-system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 46901063 # num instructions producing a value
-system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value
+system.cpu.iew.exec_nop 261908 # number of nop insts executed
+system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11601340 # Number of branches executed
+system.cpu.iew.exec_stores 12455688 # Number of stores executed
+system.cpu.iew.exec_rate 0.299278 # Inst execution rate
+system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47546734 # num instructions producing a value
+system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
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-system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads
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-system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses
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-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses
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-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
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+system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
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+system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks
-system.cpu.dcache.writebacks::total 574454 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
+system.cpu.dcache.writebacks::total 574932 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
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+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
+system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff