---------- Begin Simulation Statistics ----------
-sim_seconds 2.533141 # Number of seconds simulated
-sim_ticks 2533140518500 # Number of ticks simulated
-final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.524310 # Number of seconds simulated
+sim_ticks 2524309551500 # Number of ticks simulated
+final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 42664 # Simulator instruction rate (inst/s)
-host_op_rate 54897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1792038006 # Simulator tick rate (ticks/s)
-host_mem_usage 435912 # Number of bytes of host memory used
-host_seconds 1413.55 # Real time elapsed on the host
-sim_insts 60307702 # Number of instructions simulated
-sim_ops 77599241 # Number of ops (including micro ops) simulated
+host_inst_rate 67450 # Simulator instruction rate (inst/s)
+host_op_rate 86789 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2823365435 # Simulator tick rate (ticks/s)
+host_mem_usage 397608 # Number of bytes of host memory used
+host_seconds 894.08 # Real time elapsed on the host
+sim_insts 60305560 # Number of instructions simulated
+sim_ops 77596391 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096807 # Total number of read requests seen
-system.physmem.writeReqs 813124 # Total number of write requests seen
-system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195648 # Total number of bytes read from memory
-system.physmem.bytesWritten 52039936 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q
+system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 966197440 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533139407500 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2524308440000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154563 # Categorize read packet sizes
+system.physmem.readPktSize::6 154591 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59106 # Categorize write packet sizes
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-system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see
-system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
-system.physmem.totBankLat 16909241250 # Total cycles spent in bank access
-system.physmem.avgQLat 26044.77 # Average queueing delay per request
-system.physmem.avgBankLat 1120.08 # Average bank access latency per request
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+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
+system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
+system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
+system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
+system.physmem.avgQLat 19314.15 # Average queueing delay per request
+system.physmem.avgBankLat 1014.34 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32164.85 # Average memory access latency
-system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25328.49 # Average memory access latency
+system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.32 # Average write queue length over time
-system.physmem.readRowHits 15020284 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793162 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes
-system.physmem.avgGap 159217.50 # Average gap between requests
+system.physmem.busUtil 3.15 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 14.41 # Average write queue length over time
+system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
+system.physmem.avgGap 158662.04 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54917647 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
+system.membus.trans_dist::WriteReq 763332 # Transaction distribution
+system.membus.trans_dist::WriteResp 763332 # Transaction distribution
+system.membus.trans_dist::Writeback 59118 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138629141 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14656582 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits
+system.iobus.throughput 48301509 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121927961 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
+system.cpu.branchPred.lookups 14390442 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987438 # DTB read hits
-system.cpu.checker.dtb.read_misses 7302 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227743 # DTB write hits
+system.cpu.checker.dtb.read_hits 14986742 # DTB read hits
+system.cpu.checker.dtb.read_misses 7308 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227334 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994740 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229932 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215181 # DTB hits
-system.cpu.checker.dtb.misses 9491 # DTB misses
-system.cpu.checker.dtb.accesses 26224672 # DTB accesses
-system.cpu.checker.itb.inst_hits 61481703 # ITB inst hits
+system.cpu.checker.dtb.hits 26214076 # DTB hits
+system.cpu.checker.dtb.misses 9497 # DTB misses
+system.cpu.checker.dtb.accesses 26223573 # DTB accesses
+system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61486174 # ITB inst accesses
-system.cpu.checker.itb.hits 61481703 # DTB hits
+system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses
+system.cpu.checker.itb.hits 61479547 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61486174 # DTB accesses
-system.cpu.checker.numCycles 77885049 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61484018 # DTB accesses
+system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51396633 # DTB read hits
-system.cpu.dtb.read_misses 64067 # DTB read misses
-system.cpu.dtb.write_hits 11699653 # DTB write hits
-system.cpu.dtb.write_misses 15746 # DTB write misses
+system.cpu.dtb.read_hits 51188083 # DTB read hits
+system.cpu.dtb.read_misses 64353 # DTB read misses
+system.cpu.dtb.write_hits 11697459 # DTB write hits
+system.cpu.dtb.write_misses 15788 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51460700 # DTB read accesses
-system.cpu.dtb.write_accesses 11715399 # DTB write accesses
+system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51252436 # DTB read accesses
+system.cpu.dtb.write_accesses 11713247 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63096286 # DTB hits
-system.cpu.dtb.misses 79813 # DTB misses
-system.cpu.dtb.accesses 63176099 # DTB accesses
-system.cpu.itb.inst_hits 12325480 # ITB inst hits
-system.cpu.itb.inst_misses 11172 # ITB inst misses
+system.cpu.dtb.hits 62885542 # DTB hits
+system.cpu.dtb.misses 80141 # DTB misses
+system.cpu.dtb.accesses 62965683 # DTB accesses
+system.cpu.itb.inst_hits 11520428 # ITB inst hits
+system.cpu.itb.inst_misses 11439 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 4964 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12336652 # ITB inst accesses
-system.cpu.itb.hits 12325480 # DTB hits
-system.cpu.itb.misses 11172 # DTB misses
-system.cpu.itb.accesses 12336652 # DTB accesses
-system.cpu.numCycles 471810648 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
+system.cpu.itb.hits 11520428 # DTB hits
+system.cpu.itb.misses 11439 # DTB misses
+system.cpu.itb.accesses 11531867 # DTB accesses
+system.cpu.numCycles 473080437 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued
-system.cpu.iq.rate 0.263438 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
+system.cpu.iq.rate 0.259812 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221429 # number of nop insts executed
-system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11545908 # Number of branches executed
-system.cpu.iew.exec_stores 12211356 # Number of stores executed
-system.cpu.iew.exec_rate 0.257527 # Inst execution rate
-system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47220023 # num instructions producing a value
-system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value
+system.cpu.iew.exec_nop 221034 # number of nop insts executed
+system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11474602 # Number of branches executed
+system.cpu.iew.exec_stores 12209197 # Number of stores executed
+system.cpu.iew.exec_rate 0.255417 # Inst execution rate
+system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47030253 # num instructions producing a value
+system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458083 # Number of instructions committed
-system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60455941 # Number of instructions committed
+system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386631 # Number of memory references committed
-system.cpu.commit.loads 15654552 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961338 # Number of branches committed
+system.cpu.commit.refs 27385481 # Number of memory references committed
+system.cpu.commit.loads 15653838 # Number of loads committed
+system.cpu.commit.membars 403568 # Number of memory barriers committed
+system.cpu.commit.branches 9961054 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854854 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991262 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991205 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242306963 # The number of ROB reads
-system.cpu.rob.rob_writes 201917005 # The number of ROB writes
-system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307702 # Number of Instructions Simulated
-system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated
-system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550141266 # number of integer regfile reads
-system.cpu.int_regfile_writes 88418140 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8398 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2928 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831893 # number of misc regfile writes
-system.cpu.icache.replacements 979850 # number of replacements
-system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use
-system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits
-system.cpu.icache.overall_hits::total 11261998 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses
-system.cpu.icache.overall_misses::total 1059902 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs nan # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff