---------- Begin Simulation Statistics ----------
-sim_seconds 2.537930 # Number of seconds simulated
-sim_ticks 2537929870500 # Number of ticks simulated
-final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.526170 # Number of seconds simulated
+sim_ticks 2526169857500 # Number of ticks simulated
+final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 52642 # Simulator instruction rate (inst/s)
-host_op_rate 67714 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2204296601 # Simulator tick rate (ticks/s)
-host_mem_usage 387316 # Number of bytes of host memory used
-host_seconds 1151.36 # Real time elapsed on the host
-sim_insts 60609996 # Number of instructions simulated
-sim_ops 77962726 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory
+host_inst_rate 46796 # Simulator instruction rate (inst/s)
+host_op_rate 60213 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1960134913 # Simulator tick rate (ticks/s)
+host_mem_usage 468616 # Number of bytes of host memory used
+host_seconds 1288.77 # Real time elapsed on the host
+sim_insts 60309637 # Number of instructions simulated
+sim_ops 77601213 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096868 # Number of read requests accepted
+system.physmem.writeReqs 813159 # Number of write requests accepted
+system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 943297 # Per bank write bursts
+system.physmem.perBankRdBursts::1 937033 # Per bank write bursts
+system.physmem.perBankRdBursts::2 936962 # Per bank write bursts
+system.physmem.perBankRdBursts::3 936535 # Per bank write bursts
+system.physmem.perBankRdBursts::4 942693 # Per bank write bursts
+system.physmem.perBankRdBursts::5 936569 # Per bank write bursts
+system.physmem.perBankRdBursts::6 936319 # Per bank write bursts
+system.physmem.perBankRdBursts::7 936043 # Per bank write bursts
+system.physmem.perBankRdBursts::8 943596 # Per bank write bursts
+system.physmem.perBankRdBursts::9 936992 # Per bank write bursts
+system.physmem.perBankRdBursts::10 936414 # Per bank write bursts
+system.physmem.perBankRdBursts::11 935912 # Per bank write bursts
+system.physmem.perBankRdBursts::12 943556 # Per bank write bursts
+system.physmem.perBankRdBursts::13 937007 # Per bank write bursts
+system.physmem.perBankRdBursts::14 937039 # Per bank write bursts
+system.physmem.perBankRdBursts::15 936676 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6606 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6375 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6521 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6552 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6461 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6711 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6720 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6668 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7045 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6826 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6497 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6136 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7072 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6672 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6956 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6819 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 2526168741500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 38 # Read request sizes (log2)
+system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 154622 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 754018 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 59141 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads
+system.physmem.totQLat 571195583500 # Total ticks spent queuing
+system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks
+system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 2.99 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 14041195 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91389 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes
+system.physmem.avgGap 158778.41 # Average gap between requests
+system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 64349 # number of replacements
-system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
-system.l2c.total_refs 1931844 # Total number of references to valid blocks.
-system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
-system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
-system.l2c.Writeback_hits::total 609524 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits
-system.l2c.overall_hits::cpu.inst 977692 # number of overall hits
-system.l2c.overall_hits::cpu.data 502174 # number of overall hits
-system.l2c.overall_hits::total 1576793 # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses
-system.l2c.demand_misses::total 156282 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu.inst 12366 # number of overall misses
-system.l2c.overall_misses::cpu.data 143849 # number of overall misses
-system.l2c.overall_misses::total 156282 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 59057 # number of writebacks
-system.l2c.writebacks::total 59057 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.throughput 54878638 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149508 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149508 # Transaction distribution
+system.membus.trans_dist::WriteReq 763349 # Transaction distribution
+system.membus.trans_dist::WriteResp 763349 # Transaction distribution
+system.membus.trans_dist::Writeback 59141 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138632762 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.iobus.throughput 48266001 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121928118 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 14755327 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions.
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15052897 # DTB read hits
-system.cpu.checker.dtb.read_misses 7321 # DTB read misses
-system.cpu.checker.dtb.write_hits 11296410 # DTB write hits
-system.cpu.checker.dtb.write_misses 2195 # DTB write misses
+system.cpu.checker.dtb.read_hits 14987589 # DTB read hits
+system.cpu.checker.dtb.read_misses 7306 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227681 # DTB write hits
+system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994895 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229872 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26349307 # DTB hits
-system.cpu.checker.dtb.misses 9516 # DTB misses
-system.cpu.checker.dtb.accesses 26358823 # DTB accesses
-system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits
-system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
+system.cpu.checker.dtb.hits 26215270 # DTB hits
+system.cpu.checker.dtb.misses 9497 # DTB misses
+system.cpu.checker.dtb.accesses 26224767 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.inst_hits 61483612 # ITB inst hits
+system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses
-system.cpu.checker.itb.hits 61788771 # DTB hits
-system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61793242 # DTB accesses
-system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 61488085 # ITB inst accesses
+system.cpu.checker.itb.hits 61483612 # DTB hits
+system.cpu.checker.itb.misses 4473 # DTB misses
+system.cpu.checker.itb.accesses 61488085 # DTB accesses
+system.cpu.checker.numCycles 77887007 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51757171 # DTB read hits
-system.cpu.dtb.read_misses 78755 # DTB read misses
-system.cpu.dtb.write_hits 11824944 # DTB write hits
-system.cpu.dtb.write_misses 17612 # DTB write misses
+system.cpu.dtb.read_hits 51187284 # DTB read hits
+system.cpu.dtb.read_misses 65383 # DTB read misses
+system.cpu.dtb.write_hits 11703682 # DTB write hits
+system.cpu.dtb.write_misses 15916 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51835926 # DTB read accesses
-system.cpu.dtb.write_accesses 11842556 # DTB write accesses
+system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51252667 # DTB read accesses
+system.cpu.dtb.write_accesses 11719598 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63582115 # DTB hits
-system.cpu.dtb.misses 96367 # DTB misses
-system.cpu.dtb.accesses 63678482 # DTB accesses
-system.cpu.itb.inst_hits 13115769 # ITB inst hits
-system.cpu.itb.inst_misses 12252 # ITB inst misses
+system.cpu.dtb.hits 62890966 # DTB hits
+system.cpu.dtb.misses 81299 # DTB misses
+system.cpu.dtb.accesses 62972265 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 11527099 # ITB inst hits
+system.cpu.itb.inst_misses 11249 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13128021 # ITB inst accesses
-system.cpu.itb.hits 13115769 # DTB hits
-system.cpu.itb.misses 12252 # DTB misses
-system.cpu.itb.accesses 13128021 # DTB accesses
-system.cpu.numCycles 487049956 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11538348 # ITB inst accesses
+system.cpu.itb.hits 11527099 # DTB hits
+system.cpu.itb.misses 11249 # DTB misses
+system.cpu.itb.accesses 11538348 # DTB accesses
+system.cpu.numCycles 477119451 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued
-system.cpu.iq.rate 0.259310 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued
+system.cpu.iq.rate 0.257655 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 226495 # number of nop insts executed
-system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11753944 # Number of branches executed
-system.cpu.iew.exec_stores 12337385 # Number of stores executed
-system.cpu.iew.exec_rate 0.252721 # Inst execution rate
-system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47490892 # num instructions producing a value
-system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value
+system.cpu.iew.exec_nop 221278 # number of nop insts executed
+system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11821235 # Number of branches executed
+system.cpu.iew.exec_stores 12215513 # Number of stores executed
+system.cpu.iew.exec_rate 0.253301 # Inst execution rate
+system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47029089 # num instructions producing a value
+system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60760377 # Number of instructions committed
-system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60460018 # Number of instructions committed
+system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27521116 # Number of memory references committed
-system.cpu.commit.loads 15720306 # Number of loads committed
-system.cpu.commit.membars 413361 # Number of memory barriers committed
-system.cpu.commit.branches 10025135 # Number of branches committed
+system.cpu.commit.refs 27386851 # Number of memory references committed
+system.cpu.commit.loads 15654790 # Number of loads committed
+system.cpu.commit.membars 403577 # Number of memory barriers committed
+system.cpu.commit.branches 10306380 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69149691 # Number of committed integer instructions.
-system.cpu.commit.function_calls 996276 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69191623 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991253 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 256258159 # The number of ROB reads
-system.cpu.rob.rob_writes 209428063 # The number of ROB writes
-system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60609996 # Number of Instructions Simulated
-system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated
-system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 557221655 # number of integer regfile reads
-system.cpu.int_regfile_writes 90065137 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8220 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2852 # number of floating regfile writes
-system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads
-system.cpu.misc_regfile_writes 913466 # number of misc regfile writes
-system.cpu.icache.replacements 990831 # number of replacements
-system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use
-system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits
-system.cpu.icache.overall_hits::total 12036161 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses
-system.cpu.icache.overall_misses::total 1075440 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked
+system.cpu.rob.rob_reads 242979782 # The number of ROB reads
+system.cpu.rob.rob_writes 196005989 # The number of ROB writes
+system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60309637 # Number of Instructions Simulated
+system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated
+system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 548698002 # number of integer regfile reads
+system.cpu.int_regfile_writes 87552826 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8408 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
+system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.tags.replacements 980897 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits
+system.cpu.icache.overall_hits::total 10462766 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses
+system.cpu.icache.overall_misses::total 1060743 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 645511 # number of replacements
-system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits
-system.cpu.dcache.overall_hits::total 21154214 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses
-system.cpu.dcache.overall_misses::total 3765402 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked
+system.cpu.l2cache.tags.replacements 64391 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 51374.630920 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1887139 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 129786 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 14.540390 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 2490832751500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.305745 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000374 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 8179.061871 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 6245.594773 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.563334 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000478 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124803 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.095300 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.783915 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 65372 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3052 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6933 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54996 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997498 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 18788998 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 18788998 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53598 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10246 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 967912 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 386978 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1418734 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607635 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607635 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112878 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112878 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 53598 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10246 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 967912 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 499856 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1531612 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 53598 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10246 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 967912 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 499856 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1531612 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12357 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10744 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23148 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2913 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2913 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 12357 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143935 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156339 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 12357 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143935 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156339 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3974500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 412000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 905251250 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 810262998 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1719900748 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9827066492 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 9827066492 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3974500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 412000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 905251250 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10637329490 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 11546967240 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3974500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 412000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 905251250 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10637329490 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 11546967240 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53643 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10248 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 980269 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397722 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1441882 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607635 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607635 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2959 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2959 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246069 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246069 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53643 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10248 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 980269 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 643791 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1687951 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53643 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10248 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 980269 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 643791 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1687951 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000195 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027014 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016054 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984454 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984454 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541275 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541275 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000195 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223574 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.092621 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000195 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223574 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.092621 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 206000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.412976 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.412976 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks
+system.cpu.l2cache.writebacks::total 59141 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12342 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10679 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2913 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2913 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12342 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143870 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156259 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12342 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143870 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156259 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3417500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 749197750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 673040498 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426043248 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29132913 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29132913 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8170239508 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8170239508 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3417500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 749197750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8843280006 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9596282756 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3417500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 749197750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8843280006 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9596282756 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6814499 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17458567530 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17458567530 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6814499 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026850 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015999 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984454 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984454 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541275 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541275 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.092573 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.092573 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 193750 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements 643279 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.993228 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 21514190 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 643791 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 33.417973 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 43094250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.993228 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21020513 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21020513 # number of overall hits
+system.cpu.dcache.overall_hits::total 21020513 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 736359 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 736359 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2962417 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2962417 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13527 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3698776 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3698776 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3698776 # number of overall misses
+system.cpu.dcache.overall_misses::total 3698776 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149727245915 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14497007 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14497007 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222282 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222282 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256525 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256525 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247610 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247610 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24719289 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks
-system.cpu.dcache.writebacks::total 609524 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks
+system.cpu.dcache.writebacks::total 607635 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs nan # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses 0 # Number of tag accesses
+system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff