stats: Update stats for DRAM changes

[gem5.git] / tests / long / fs / 10.linux-boot / ref / arm / linux / realview-o3-checker / stats.txt

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 8cfdfc3f7e54f3a3b4b1989120d94e222773f113..5f9799ffedad1da87b43de8165911f8a502eaab8 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,135 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.525141                       # Number of seconds simulated
-sim_ticks                                2525141046500                       # Number of ticks simulated
-final_tick                               2525141046500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.526170                       # Number of seconds simulated
+sim_ticks                                2526169857500                       # Number of ticks simulated
+final_tick                               2526169857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50522                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65007                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2115457252                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 427804                       # Number of bytes of host memory used
-host_seconds                                  1193.66                       # Real time elapsed on the host
-sim_insts                                    60305756                       # Number of instructions simulated
-sim_ops                                      77596741                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  46796                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60213                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1960134913                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 468616                       # Number of bytes of host memory used
+host_seconds                                  1288.77                       # Real time elapsed on the host
+sim_insts                                    60309637                       # Number of instructions simulated
+sim_ops                                      77601213                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094416                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129432144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3784000                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            797632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9095320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129433624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6800072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           41                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12457                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142134                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096843                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59125                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142150                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096868                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813143                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47339005                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             76                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315724                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3601548                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51257392                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315724                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315724                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1498530                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1194417                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2692947                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1498530                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47339005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            76                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315724                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4795965                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53950339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096843                       # Number of read requests accepted
-system.physmem.writeReqs                       813143                       # Number of write requests accepted
-system.physmem.readBursts                    15096843                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813143                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                963738752                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   2459200                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6902144                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129432144                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6800072                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    38425                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  705284                       # Number of DRAM write bursts merged with an existing one
+system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47319725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1140                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3600439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51237103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1498325                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1193931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2692256                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1498325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47319725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1140                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              315748                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4794370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53929359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15096868                       # Number of read requests accepted
+system.physmem.writeReqs                       813159                       # Number of write requests accepted
+system.physmem.readBursts                    15096868                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                960809152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   5390400                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6824768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 129433624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    84225                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706499                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs           4674                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943582                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              943145                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              939291                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              939307                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              943115                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              943141                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              939138                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              938546                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943996                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              943390                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             938426                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             937974                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943928                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             943533                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             939234                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             938672                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6704                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6457                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6598                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6635                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6561                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6794                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6789                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6723                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7136                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6877                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6538                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6183                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7149                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6765                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7038                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6899                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              943297                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              937033                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              936962                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              936535                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              942693                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              936569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              936319                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              936043                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              943596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              936992                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             936414                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             935912                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             943556                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             937007                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             937039                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             936676                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6606                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6375                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6521                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6552                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6461                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6711                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6720                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6668                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7045                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6826                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6497                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6136                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6672                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6956                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6819                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2525139929000                       # Total gap between requests
+system.physmem.totGap                    2526168741500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      36                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154599                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154622                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59125                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1163754                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1108384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1064134                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3627605                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2618920                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2606295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2613037                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     53652                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     58180                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     21151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20926                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20516                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20376                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20256                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      255                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1044851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    985737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    938636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    947948                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    933228                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    933834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2717841                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2709185                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3589675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     37568                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    33871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    34960                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    32201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    30053                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    21726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21191                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -142,604 +144,147 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5443                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4887                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5096                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        86114                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11271.566528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1003.490719                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16771.547354                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23576     27.38%     27.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14050     16.32%     43.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2599      3.02%     46.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2090      2.43%     49.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1311      1.52%     50.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1239      1.44%     52.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          869      1.01%     53.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1005      1.17%     54.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          571      0.66%     54.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          602      0.70%     55.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          523      0.61%     56.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          509      0.59%     56.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          284      0.33%     57.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          276      0.32%     57.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          154      0.18%     57.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          642      0.75%     58.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095           97      0.11%     58.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          141      0.16%     58.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           78      0.09%     58.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          123      0.14%     58.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           49      0.06%     58.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          518      0.60%     59.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           29      0.03%     59.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          316      0.37%     59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           18      0.02%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671          102      0.12%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           18      0.02%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          211      0.25%     60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           23      0.03%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           55      0.06%     60.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           13      0.02%     60.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          327      0.38%     60.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119            6      0.01%     60.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           31      0.04%     60.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           13      0.02%     60.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311          124      0.14%     61.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375            3      0.00%     61.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           17      0.02%     61.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503            9      0.01%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           99      0.11%     61.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            7      0.01%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           25      0.03%     61.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759           11      0.01%     61.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           90      0.10%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887            6      0.01%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           23      0.03%     61.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            2      0.00%     61.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          292      0.34%     61.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            7      0.01%     61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           16      0.02%     61.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            8      0.01%     61.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           98      0.11%     61.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            9      0.01%     61.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           18      0.02%     61.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527            8      0.01%     61.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591           97      0.11%     62.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            4      0.00%     62.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           12      0.01%     62.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783            7      0.01%     62.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847          158      0.18%     62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911            9      0.01%     62.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           14      0.02%     62.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039           10      0.01%     62.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          373      0.43%     62.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            4      0.00%     62.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           16      0.02%     62.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            8      0.01%     62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359          116      0.13%     62.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           14      0.02%     62.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           12      0.01%     62.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            8      0.01%     62.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           99      0.11%     63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            3      0.00%     63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            8      0.01%     63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            2      0.00%     63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           19      0.02%     63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            2      0.00%     63.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999           13      0.02%     63.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            5      0.01%     63.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          426      0.49%     63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            5      0.01%     63.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255            8      0.01%     63.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            6      0.01%     63.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           28      0.03%     63.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447           11      0.01%     63.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           19      0.02%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            3      0.00%     63.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           89      0.10%     63.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            1      0.00%     63.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767           10      0.01%     63.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            2      0.00%     63.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          131      0.15%     63.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            1      0.00%     63.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023           15      0.02%     63.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087           11      0.01%     64.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          413      0.48%     64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            1      0.00%     64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279            8      0.01%     64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            2      0.00%     64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           87      0.10%     64.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            4      0.00%     64.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535           12      0.01%     64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            5      0.01%     64.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663          145      0.17%     64.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727            1      0.00%     64.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791           14      0.02%     64.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            7      0.01%     64.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           24      0.03%     64.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            2      0.00%     64.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            8      0.01%     64.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            4      0.00%     64.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          363      0.42%     65.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            3      0.00%     65.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303            9      0.01%     65.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367           12      0.01%     65.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           84      0.10%     65.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7495            5      0.01%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559           10      0.01%     65.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            1      0.00%     65.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           98      0.11%     65.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            3      0.00%     65.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            9      0.01%     65.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7879            5      0.01%     65.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           82      0.10%     65.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            1      0.00%     65.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071           13      0.02%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8135            1      0.00%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          508      0.59%     66.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8263            1      0.00%     66.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8320-8327            1      0.00%     66.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           76      0.09%     66.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8647            1      0.00%     66.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           89      0.10%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8839            1      0.00%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8903            1      0.00%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967           74      0.09%     66.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          350      0.41%     66.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9351            1      0.00%     66.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           17      0.02%     66.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9543            1      0.00%     66.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9607            3      0.00%     66.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9671            1      0.00%     66.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735          138      0.16%     67.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9799            1      0.00%     67.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9863            1      0.00%     67.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           79      0.09%     67.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10119            6      0.01%     67.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          402      0.47%     67.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10432-10439            1      0.00%     67.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503           84      0.10%     67.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10560-10567            1      0.00%     67.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           76      0.09%     67.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10951            3      0.00%     67.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           15      0.02%     67.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            1      0.00%     67.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          416      0.48%     68.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11399            1      0.00%     68.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527           13      0.02%     68.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11591            2      0.00%     68.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11719            2      0.00%     68.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           84      0.10%     68.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11968-11975            1      0.00%     68.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           98      0.11%     68.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12167            5      0.01%     68.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          335      0.39%     69.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12423            3      0.00%     69.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            1      0.00%     69.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551          141      0.16%     69.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807           79      0.09%     69.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12871            1      0.00%     69.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063           86      0.10%     69.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13127            1      0.00%     69.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            4      0.00%     69.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          286      0.33%     69.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           76      0.09%     69.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           74      0.09%     69.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13888-13895            1      0.00%     69.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           91      0.11%     70.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            3      0.00%     70.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          284      0.33%     70.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14471            2      0.00%     70.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599          139      0.16%     70.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14727            4      0.00%     70.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855          146      0.17%     70.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14919            2      0.00%     70.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           13      0.02%     70.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15175            1      0.00%     70.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            2      0.00%     70.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15303            2      0.00%     70.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          405      0.47%     71.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           17      0.02%     71.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15687            1      0.00%     71.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879           80      0.09%     71.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16071            1      0.00%     71.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           74      0.09%     71.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263           11      0.01%     71.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          645      0.75%     72.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           72      0.08%     72.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16704-16711            2      0.00%     72.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16839            1      0.00%     72.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903           78      0.09%     72.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17088-17095            1      0.00%     72.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           28      0.03%     72.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            5      0.01%     72.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          407      0.47%     72.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17472-17479            1      0.00%     72.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17536-17543            2      0.00%     72.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           18      0.02%     72.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17735            2      0.00%     72.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17792-17799            3      0.00%     72.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17856-17863            1      0.00%     72.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927          147      0.17%     73.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17984-17991            1      0.00%     73.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18055            2      0.00%     73.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            2      0.00%     73.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183          144      0.17%     73.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            4      0.00%     73.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          279      0.32%     73.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18496-18503            1      0.00%     73.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           89      0.10%     73.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18880-18887            2      0.00%     73.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           73      0.08%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19136-19143            1      0.00%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           77      0.09%     73.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            5      0.01%     73.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          263      0.31%     74.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19520-19527            1      0.00%     74.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           82      0.10%     74.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975           79      0.09%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20096-20103            1      0.00%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231          140      0.16%     74.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20295            1      0.00%     74.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            3      0.00%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          343      0.40%     74.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           96      0.11%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20864-20871            2      0.00%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           82      0.10%     75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21120-21127            1      0.00%     75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           14      0.02%     75.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21312-21319            1      0.00%     75.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            4      0.00%     75.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          401      0.47%     75.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21568-21575            1      0.00%     75.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21632-21639            1      0.00%     75.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           17      0.02%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21888-21895            2      0.00%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           77      0.09%     75.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22144-22151            1      0.00%     75.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279           84      0.10%     75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            3      0.00%     75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22464-22471            1      0.00%     75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          400      0.46%     76.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22720-22727            2      0.00%     76.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           80      0.09%     76.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22848-22855            1      0.00%     76.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22912-22919            1      0.00%     76.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22976-22983            2      0.00%     76.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047          136      0.16%     76.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23104-23111            1      0.00%     76.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           21      0.02%     76.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23360-23367            3      0.00%     76.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            2      0.00%     76.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          351      0.41%     76.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23680-23687            2      0.00%     76.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           73      0.08%     77.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23936-23943            1      0.00%     77.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24000-24007            2      0.00%     77.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           83      0.10%     77.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24256-24263            1      0.00%     77.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           83      0.10%     77.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24448-24455            4      0.00%     77.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          387      0.45%     77.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           78      0.09%     77.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24960-24967            1      0.00%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25024-25031            1      0.00%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           89      0.10%     77.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25280-25287            1      0.00%     77.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351           72      0.08%     77.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            4      0.00%     77.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          349      0.41%     78.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           19      0.02%     78.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25984-25991            3      0.00%     78.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119          133      0.15%     78.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26176-26183            1      0.00%     78.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            1      0.00%     78.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26311            2      0.00%     78.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           78      0.09%     78.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            1      0.00%     78.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          401      0.47%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26688-26695            1      0.00%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            2      0.00%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26816-26823            1      0.00%     79.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887           82      0.10%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            2      0.00%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           77      0.09%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27200-27207            1      0.00%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           15      0.02%     79.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27584-27591            1      0.00%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          403      0.47%     79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            1      0.00%     79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           11      0.01%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27968-27975            2      0.00%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28032-28039            1      0.00%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28096-28103            1      0.00%     79.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           83      0.10%     79.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            2      0.00%     79.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28352-28359            1      0.00%     79.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           97      0.11%     80.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28480-28487            2      0.00%     80.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            2      0.00%     80.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            1      0.00%     80.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          341      0.40%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28736-28743            1      0.00%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28800-28807            1      0.00%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28864-28871            2      0.00%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935          143      0.17%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28992-28999            1      0.00%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29056-29063            1      0.00%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191           77      0.09%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29248-29255            2      0.00%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447           85      0.10%     80.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29504-29511            3      0.00%     80.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            2      0.00%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29632-29639            1      0.00%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          268      0.31%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           76      0.09%     81.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215           74      0.09%     81.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30336-30343            2      0.00%     81.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           92      0.11%     81.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            4      0.00%     81.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30656-30663            1      0.00%     81.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          271      0.31%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30784-30791            1      0.00%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30855            2      0.00%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30912-30919            1      0.00%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983          145      0.17%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31104-31111            2      0.00%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239          148      0.17%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31296-31303            1      0.00%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31360-31367            1      0.00%     82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           19      0.02%     82.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31552-31559            2      0.00%     82.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            5      0.01%     82.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31680-31687            4      0.00%     82.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          398      0.46%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31879            1      0.00%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31936-31943            1      0.00%     82.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           18      0.02%     82.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32128-32135            1      0.00%     82.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263           78      0.09%     82.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32320-32327            1      0.00%     82.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32448-32455            1      0.00%     82.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           83      0.10%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32576-32583            1      0.00%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          642      0.75%     83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32832-32839            2      0.00%     83.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           73      0.08%     83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33216-33223            2      0.00%     83.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287           78      0.09%     83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            4      0.00%     83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           27      0.03%     83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            2      0.00%     83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          406      0.47%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33856-33863            1      0.00%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33920-33927            1      0.00%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33984-33991            1      0.00%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           16      0.02%     84.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311          144      0.17%     84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            2      0.00%     84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567          147      0.17%     84.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          269      0.31%     84.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34944-34951            1      0.00%     84.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           87      0.10%     85.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35136-35143            1      0.00%     85.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335           72      0.08%     85.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35456-35463            2      0.00%     85.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           77      0.09%     85.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35712-35719            1      0.00%     85.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          268      0.31%     85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35968-35975            1      0.00%     85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103           81      0.09%     85.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36224-36231            2      0.00%     85.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359           77      0.09%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            1      0.00%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615          144      0.17%     85.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36736-36743            2      0.00%     85.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          338      0.39%     86.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36992-36999            1      0.00%     86.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           91      0.11%     86.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37248-37255            1      0.00%     86.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           83      0.10%     86.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            2      0.00%     86.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37568-37575            1      0.00%     86.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           11      0.01%     86.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          404      0.47%     86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37952-37959            1      0.00%     86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38016-38023            2      0.00%     86.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           15      0.02%     86.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38272-38279            1      0.00%     86.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38336-38343            1      0.00%     86.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           77      0.09%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            1      0.00%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663           84      0.10%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38720-38727            1      0.00%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          401      0.47%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38976-38983            1      0.00%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39040-39047            2      0.00%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39104-39111            1      0.00%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           77      0.09%     87.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39232-39239            1      0.00%     87.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431          130      0.15%     87.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            1      0.00%     87.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           15      0.02%     87.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39808-39815            1      0.00%     87.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          348      0.40%     88.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40064-40071            3      0.00%     88.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199           71      0.08%     88.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           86      0.10%     88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            3      0.00%     88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40640-40647            1      0.00%     88.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           78      0.09%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          387      0.45%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            2      0.00%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           78      0.09%     89.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41344-41351            2      0.00%     89.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41408-41415            1      0.00%     89.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           83      0.10%     89.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           72      0.08%     89.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41856-41863            3      0.00%     89.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          347      0.40%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42112-42119            2      0.00%     89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           18      0.02%     89.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42368-42375            1      0.00%     89.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503          133      0.15%     89.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            3      0.00%     89.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42688-42695            1      0.00%     89.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           79      0.09%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42816-42823            1      0.00%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          399      0.46%     90.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271           82      0.10%     90.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43328-43335            1      0.00%     90.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           76      0.09%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            2      0.00%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           20      0.02%     90.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43840-43847            2      0.00%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43904-43911            2      0.00%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          403      0.47%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44224-44231            1      0.00%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295           10      0.01%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44352-44359            1      0.00%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44416-44423            1      0.00%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           81      0.09%     91.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44672-44679            3      0.00%     91.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           96      0.11%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44864-44871            1      0.00%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44928-44935            1      0.00%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          341      0.40%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45248-45255            1      0.00%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319          143      0.17%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45440-45447            1      0.00%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575           82      0.10%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            5      0.01%     92.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           84      0.10%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45888-45895            1      0.00%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          261      0.30%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46144-46151            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           73      0.08%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           68      0.08%     92.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           91      0.11%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46912-46919            1      0.00%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46976-46983            2      0.00%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          272      0.32%     93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47168-47175            1      0.00%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47232-47239            2      0.00%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            3      0.00%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367          142      0.16%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623          144      0.17%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            4      0.00%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47808-47815            1      0.00%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           25      0.03%     93.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47936-47943            2      0.00%     93.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48000-48007            1      0.00%     93.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          395      0.46%     93.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           16      0.02%     93.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647           76      0.09%     93.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           71      0.08%     94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           72      0.08%     94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            1      0.00%     94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            3      0.00%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5013      5.82%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49216-49223            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49600-49607            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49664-49671            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49728-49735            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49856-49863            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49920-49927            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50368-50375            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50496-50503            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50560-50567            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50688-50695            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50944-50951            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51008-51015            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51136-51143            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51207            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51264-51271            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51463            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51520-51527            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51840-51847            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          86114                       # Bytes accessed per row activation
-system.physmem.totQLat                   365610387500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              458189280000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75292090000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 17286802500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24279.47                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1147.98                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6039                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       949853                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1012.832967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     998.129194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      95.600820                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           4614      0.49%      0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3555      0.37%      0.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1868      0.20%      1.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1270      0.13%      1.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          998      0.11%      1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          697      0.07%      1.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          628      0.07%      1.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          802      0.08%      1.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       935421     98.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         949853                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5541                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2709.372676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    121858.968991                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         5537     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5541                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5541                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.245082                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.302826                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.619957                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3691     66.61%     66.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.29%     66.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                178      3.21%     70.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1008     18.19%     88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 44      0.79%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 25      0.45%     89.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 20      0.36%     89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 16      0.29%     90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.09%     90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.04%     90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.02%     90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%     90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  2      0.04%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.02%     90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                143      2.58%     93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                305      5.50%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 21      0.38%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 14      0.25%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 20      0.36%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 15      0.27%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  5      0.09%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5541                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   571195583500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              674382869750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  75063215000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 28124071250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       38047.64                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1873.36                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30427.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.66                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44921.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14986740                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93410                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  86.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158714.15                       # Average gap between requests
-system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.73                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         7.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14041195                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91389                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158778.41                       # Average gap between requests
+system.physmem.pageHitRate                      93.47                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.34                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -752,63 +297,63 @@ system.realview.nvmem.bw_inst_read::cpu.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54899945                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149440                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149440                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763332                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763332                       # Transaction distribution
-system.membus.trans_dist::Writeback             59125                       # Transaction distribution
+system.membus.throughput                     54878638                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16149508                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16149508                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
+system.membus.trans_dist::Writeback             59141                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4674                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131442                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131442                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382942                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq            131433                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131433                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885779                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272485                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272653                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34156901                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390301                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34157069                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16694552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19092441                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095098                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138630105                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138630105                       # Total data (bytes)
+system.membus.tot_pkt_size::total           138632762                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              138632762                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1486773500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1487078000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3686000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3653000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17363455000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17362845500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4733701508                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4737809043                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        33738367951                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37210156152                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48285606                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16125522                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16125522                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8157                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8157                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      48266001                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8174                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7936                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          516                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1024                       # Packet count per connected master and slave (bytes)
@@ -831,11 +376,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382942                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383044                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     29884416                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     29884416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32267358                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                32267460                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15872                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1032                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2048                       # Cumulative packet size per connected master and slave (bytes)
@@ -858,12 +403,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390301                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            121927965                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               121927965                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total            121928118                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               121928118                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy              3973000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -911,42 +456,85 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         14942208000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374785000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         40921194049                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
-system.cpu.branchPred.lookups                14384905                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11471084                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            703956                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9467627                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7657685                       # Number of BTB hits
+system.iobus.respLayer1.occupancy         37245686848                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                14755327                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11837490                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            706705                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9530563                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7665782                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.882834                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1397242                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72494                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.433674                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1400618                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              72971                       # Number of incorrect RAS predictions.
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             14986852                       # DTB read hits
+system.cpu.checker.dtb.read_hits             14987589                       # DTB read hits
 system.cpu.checker.dtb.read_misses               7306                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11227410                       # DTB write hits
+system.cpu.checker.dtb.write_hits            11227681                       # DTB write hits
 system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             6418                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             3398                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults            179                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults            180                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         14994158                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11229601                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         14994895                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11229872                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26214262                       # DTB hits
+system.cpu.checker.dtb.hits                  26215270                       # DTB hits
 system.cpu.checker.dtb.misses                    9497                       # DTB misses
-system.cpu.checker.dtb.accesses              26223759                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61479743                       # ITB inst hits
-system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
+system.cpu.checker.dtb.accesses              26224767                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.itb.inst_hits             61483612                       # ITB inst hits
+system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -955,43 +543,85 @@ system.cpu.checker.itb.flush_tlb                    4                       # Nu
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries             2372                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         61484214                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61479743                       # DTB hits
-system.cpu.checker.itb.misses                    4471                       # DTB misses
-system.cpu.checker.itb.accesses              61484214                       # DTB accesses
-system.cpu.checker.numCycles                 77882535                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses         61488085                       # ITB inst accesses
+system.cpu.checker.itb.hits                  61483612                       # DTB hits
+system.cpu.checker.itb.misses                    4473                       # DTB misses
+system.cpu.checker.itb.accesses              61488085                       # DTB accesses
+system.cpu.checker.numCycles                 77887007                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51179212                       # DTB read hits
-system.cpu.dtb.read_misses                      64531                       # DTB read misses
-system.cpu.dtb.write_hits                    11698539                       # DTB write hits
-system.cpu.dtb.write_misses                     15837                       # DTB write misses
+system.cpu.dtb.read_hits                     51187284                       # DTB read hits
+system.cpu.dtb.read_misses                      65383                       # DTB read misses
+system.cpu.dtb.write_hits                    11703682                       # DTB write hits
+system.cpu.dtb.write_misses                     15916                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     6568                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2411                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    405                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3484                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2464                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    408                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1396                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51243743                       # DTB read accesses
-system.cpu.dtb.write_accesses                11714376                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51252667                       # DTB read accesses
+system.cpu.dtb.write_accesses                11719598                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62877751                       # DTB hits
-system.cpu.dtb.misses                           80368                       # DTB misses
-system.cpu.dtb.accesses                      62958119                       # DTB accesses
-system.cpu.itb.inst_hits                     11513998                       # ITB inst hits
-system.cpu.itb.inst_misses                      11344                       # ITB inst misses
+system.cpu.dtb.hits                          62890966                       # DTB hits
+system.cpu.dtb.misses                           81299                       # DTB misses
+system.cpu.dtb.accesses                      62972265                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                     11527099                       # ITB inst hits
+system.cpu.itb.inst_misses                      11249                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -1000,551 +630,571 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     4962                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2504                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2968                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2978                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11525342                       # ITB inst accesses
-system.cpu.itb.hits                          11513998                       # DTB hits
-system.cpu.itb.misses                           11344                       # DTB misses
-system.cpu.itb.accesses                      11525342                       # DTB accesses
-system.cpu.numCycles                        474882944                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 11538348                       # ITB inst accesses
+system.cpu.itb.hits                          11527099                       # DTB hits
+system.cpu.itb.misses                           11249                       # DTB misses
+system.cpu.itb.accesses                      11538348                       # DTB accesses
+system.cpu.numCycles                        477119451                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29745457                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90266235                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14384905                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9054927                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20140969                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4652912                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     123687                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               96003967                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2624                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         87891                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2685420                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          468                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11510536                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                707949                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5425                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          151996950                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.740543                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.094686                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29745347                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90343663                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14755327                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9066400                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20160515                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4659374                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     121718                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98274067                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2638                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         88444                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      2690508                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          430                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11523637                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                709778                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5230                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.730147                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.081756                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                131871277     86.76%     86.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1302073      0.86%     87.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1710886      1.13%     88.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2295409      1.51%     90.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2102442      1.38%     91.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1107607      0.73%     92.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2555872      1.68%     94.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   743971      0.49%     94.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8307413      5.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                134149007     86.94%     86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1305162      0.85%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1712027      1.11%     88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2298089      1.49%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2109453      1.37%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1103374      0.72%     92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2555030      1.66%     94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   746204      0.48%     94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8315700      5.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            151996950                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.030291                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.190081                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31502209                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              98125273                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18366247                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                966197                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3037024                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1956644                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171990                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              107262918                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                568386                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3037024                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33252800                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39466554                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       52672825                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17523888                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6043859                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102275198                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 20557                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1004739                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4063584                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              673                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           106014240                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             466907038                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        432047963                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10635                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78387438                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27626801                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             830029                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         736499                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12184256                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19715159                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13304037                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1977063                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2478152                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95106473                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1982467                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122897190                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            166901                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18919534                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     47250176                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         500160                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     151996950                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.808550                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.527901                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.030926                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.189352                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 31777956                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100129696                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18080387                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1265250                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3040757                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1958128                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172070                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              107328179                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                570705                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3040757                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33516419                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38693091                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55142047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17591419                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6310313                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102323009                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   472                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1000039                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4066050                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           106393961                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             474042454                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        432890289                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10421                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78727775                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27666185                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1171025                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1077190                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12642564                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19725934                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13308899                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1965192                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2472766                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   95138203                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1987496                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 122932074                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165549                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18954995                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47273204                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         505173                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154294046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.796739                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.515436                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           108284402     71.24%     71.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13439431      8.84%     80.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6944257      4.57%     84.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5857722      3.85%     88.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12372410      8.14%     96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2808060      1.85%     98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1695891      1.12%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              467423      0.31%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              127354      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           109928517     71.25%     71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14405522      9.34%     80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6874407      4.46%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5677816      3.68%     88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12311103      7.98%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2805861      1.82%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1693952      1.10%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              468083      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128785      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       151996950                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154294046                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   62444      0.71%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      7      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8371933     94.63%     95.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                412257      4.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61713      0.70%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8365366     94.65%     95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                411034      4.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            363666      0.30%      0.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57615534     46.88%     47.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93100      0.08%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  33      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  3      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              25      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2115      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           25      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52504661     42.72%     89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12318028     10.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57971139     47.16%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                93360      0.08%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  25      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              18      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             52513425     42.72%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12323457     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122897190                       # Type of FU issued
-system.cpu.iq.rate                           0.258795                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8846641                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071984                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          406861293                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         116024937                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85463742                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23592                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12620                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10347                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131367569                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12596                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           623590                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              122932074                       # Type of FU issued
+system.cpu.iq.rate                           0.257655                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8838117                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.071894                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          409219406                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         116097301                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85490758                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               23382                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10288                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              131729199                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12474                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           624027                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4061151                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6344                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        30249                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1572309                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4071144                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6793                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30196                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1576838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107765                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        681284                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107946                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        680806                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3037024                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30702730                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                434457                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97310809                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            203906                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19715159                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13304037                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1409970                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 113496                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3538                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          30249                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         349429                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       269322                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               618751                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120821579                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51866256                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2075611                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3040757                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30225758                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                434257                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97346977                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            205962                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19725934                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13308899                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1415361                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3429                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30196                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         351437                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       270055                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               621492                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             120854906                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              51874598                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2077168                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221869                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64076774                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11475076                       # Number of branches executed
-system.cpu.iew.exec_stores                   12210518                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.254424                       # Inst execution rate
-system.cpu.iew.wb_sent                      119883669                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85474089                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47026181                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87876552                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        221278                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64090111                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11821235                       # Number of branches executed
+system.cpu.iew.exec_stores                   12215513                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253301                       # Inst execution rate
+system.cpu.iew.wb_sent                      119911072                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85501046                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47029089                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  87607932                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179990                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.535139                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179203                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536813                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        18658160                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482307                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            534513                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    148959926                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.521933                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.510472                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        18687715                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1482323                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            537083                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.514049                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.489960                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    121529130     81.59%     81.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13302723      8.93%     90.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3899356      2.62%     93.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2115942      1.42%     94.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1939571      1.30%     95.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       978607      0.66%     96.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1596110      1.07%     97.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       718014      0.48%     98.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2880473      1.93%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122784132     81.18%     81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14644365      9.68%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3917692      2.59%     93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2132798      1.41%     94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1620432      1.07%     95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       975760      0.65%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1598249      1.06%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       715459      0.47%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2864402      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    148959926                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60456137                       # Number of instructions committed
-system.cpu.commit.committedOps               77747122                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60460018                       # Number of instructions committed
+system.cpu.commit.committedOps               77751594                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27385736                       # Number of memory references committed
-system.cpu.commit.loads                      15654008                       # Number of loads committed
-system.cpu.commit.membars                      403573                       # Number of memory barriers committed
-system.cpu.commit.branches                    9961077                       # Number of branches committed
+system.cpu.commit.refs                       27386851                       # Number of memory references committed
+system.cpu.commit.loads                      15654790                       # Number of loads committed
+system.cpu.commit.membars                      403577                       # Number of memory barriers committed
+system.cpu.commit.branches                   10306380                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  68852562                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991208                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2880473                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69191623                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991253                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2864402                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    240636318                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195934369                       # The number of ROB writes
-system.cpu.timesIdled                         1776906                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       322885994                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575316115                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60305756                       # Number of Instructions Simulated
-system.cpu.committedOps                      77596741                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60305756                       # Number of Instructions Simulated
-system.cpu.cpi                               7.874587                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.874587                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126991                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126991                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                547208472                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87526189                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8624                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     3008                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                30165107                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 831837                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58889875                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2658094                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2658093                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763332                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763332                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607699                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2955                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2967                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246142                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246142                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961671                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796233                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31091                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128199                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7917194                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62737088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85515993                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        43120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148510785                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148510785                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       194456                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3128799181                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                    242979782                       # The number of ROB reads
+system.cpu.rob.rob_writes                   196005989                       # The number of ROB writes
+system.cpu.timesIdled                         1777234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       322825405                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4575137230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60309637                       # Number of Instructions Simulated
+system.cpu.committedOps                      77601213                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60309637                       # Number of Instructions Simulated
+system.cpu.cpi                               7.911164                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.911164                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.126404                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.126404                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                548698002                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87552826                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8408                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2932                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               268236665                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173235                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                58867266                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2659080                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2659079                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       607635                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2959                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2975                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246069                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961962                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796085                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30498                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129069                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7917614                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62744960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85505466                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214572                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148505990                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148505990                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       202724                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3129185667                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1474440753                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1474638965                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2550199081                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2549207556                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      20321978                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      20255489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74655295                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75530794                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            980741                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.579116                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10449649                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            981253                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.649291                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6918450250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.579116                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999178                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999178                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     10449649                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10449649                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10449649                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10449649                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10449649                       # number of overall hits
-system.cpu.icache.overall_hits::total        10449649                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1060761                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1060761                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1060761                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1060761                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1060761                       # number of overall misses
-system.cpu.icache.overall_misses::total       1060761                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14273214680                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14273214680                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14273214680                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14273214680                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14273214680                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14273214680                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11510410                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11510410                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11510410                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11510410                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11510410                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11510410                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092157                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092157                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092157                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092157                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092157                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092157                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13455.636736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13455.636736                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         6677                       # number of cycles access was blocked
+system.cpu.icache.tags.replacements            980897                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.570903                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            10462766                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            981409                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             10.660964                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6958078250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.570903                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          12504958                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12504958                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     10462766                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10462766                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10462766                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10462766                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10462766                       # number of overall hits
+system.cpu.icache.overall_hits::total        10462766                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1060743                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1060743                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1060743                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1060743                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1060743                       # number of overall misses
+system.cpu.icache.overall_misses::total       1060743                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14268635888                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14268635888                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.092050                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.092050                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.092050                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.092050                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7798                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               323                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               344                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.671827                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.668605                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79476                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        79476                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        79476                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        79476                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        79476                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        79476                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981285                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       981285                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       981285                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       981285                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       981285                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       981285                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587356987                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11587356987                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587356987                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11587356987                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587356987                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11587356987                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8658250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8658250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8658250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      8658250                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085252                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085252                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085252                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.085252                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085252                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.085252                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        79293                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        79293                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       981450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       981450                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total       981450                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64371                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51366.694603                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1888244                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129769                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.550810                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490009951000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    27.934134                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.003945                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8175.587712                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6237.500172                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563441                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000426                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            64391                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51374.630920                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1887139                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129786                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.540390                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2490832751500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.305745                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8179.061871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6245.594773                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000478                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124750                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095177                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783794                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53605                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10777                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       967799                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       387031                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1419212                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607699                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607699                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           40                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           40                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112944                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112944                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        53605                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10777                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       967799                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       499975                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1532156                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        53605                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10777                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       967799                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       499975                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1532156                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           41                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12350                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10721                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23115                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2915                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2915                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095300                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.783915                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65372                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3052                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997498                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18788998                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18788998                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53598                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10246                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        1418734                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       607635                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       607635                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       112878                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       112878                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53598                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::cpu.inst       967912                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       499856                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1531612                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53598                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10246                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       967912                       # number of overall hits
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+system.cpu.l2cache.overall_hits::total        1531612                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12357                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        10744                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23148                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2913                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2913                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133198                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133198                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           41                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12350                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143919                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156313                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           41                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            3                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12350                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143919                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156313                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3352500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       233000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    906466500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    812441248                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1722493248                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10117185994                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10117185994                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3352500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       233000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    906466500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10929627242                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11839679242                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3352500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       233000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    906466500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10929627242                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11839679242                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53646                       # number of ReadReq accesses(hits+misses)
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1553,109 +1203,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59125                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59125                       # number of writebacks
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 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12342                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143870                       # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       387500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    749197750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    673040498                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426043248                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29132913                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29132913                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8456317006                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8456317006                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2846500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       196000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    750549750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9131817754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9885410004                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2846500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       196000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    750549750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9131817754                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9885410004                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6187249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17442637817                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17442637817                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6187249                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000764                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000278                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012589                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026791                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015973                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986464                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986464                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541143                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541143                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000764                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000278                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012589                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223413                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092532                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000764                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000278                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012589                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223413                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092532                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       387500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    749197750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8843280006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9596282756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    749197750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8843280006                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9596282756                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6814499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6814499                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026850                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015999                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for demand accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::total     0.092573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.092573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408                       # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1665,161 +1315,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643382                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993331                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21503755                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            643894                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.396421                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          42430250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993331                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            643279                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.993228                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21514190                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            643791                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             33.417973                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          43094250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.993228                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13751955                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13751955                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7258296                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7258296                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242828                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242828                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21010251                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21010251                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21010251                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21010251                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       737736                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        737736                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2963735                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2963735                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13555                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13555                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3701471                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3701471                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3701471                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3701471                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10012711310                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10012711310                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 141368125836                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185715250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    185715250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 151380837146                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 151380837146                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 151380837146                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 151380837146                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14489691                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14489691                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222031                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222031                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256383                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256383                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24711722                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24711722                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24711722                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24711722                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050915                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050915                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289936                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289936                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052870                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052870                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.149786                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.149786                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.149786                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.149786                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40897.480257                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40897.480257                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33174                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        27500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2643                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             285                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.551646                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    96.491228                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         101537487                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101537487                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13760648                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13760648                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7259865                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7259865                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21020513                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21020513                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21020513                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21020513                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       736359                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        736359                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2962417                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2962417                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           16                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           16                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3698776                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3698776                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3698776                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3698776                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149727245915                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149727245915                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        31777                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        23524                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             274                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.050436                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    85.854015                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607699                       # number of writebacks
-system.cpu.dcache.writebacks::total            607699                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       352116                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       352116                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2714717                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2714717                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1344                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1344                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3066833                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3066833                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3066833                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3066833                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385620                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385620                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249018                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       249018                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12211                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12211                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634638                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634638                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634638                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634638                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4970319128                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4970319128                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11601864538                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11601864538                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    146011000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    146011000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16572183666                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16572183666                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16572183666                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16572183666                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26841518267                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26841518267                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026613                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026613                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024361                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024361                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047628                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047628                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025682                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025682                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607635                       # number of writebacks
+system.cpu.dcache.writebacks::total            607635                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3064204                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3064204                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634572                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634572                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1833,6 +1490,8 @@ system.iocache.tags.total_refs                      0                       # To
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1841,10 +1500,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1499087755049                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1715151162848                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency