---------- Begin Simulation Statistics ----------
-sim_seconds 2.523205 # Number of seconds simulated
-sim_ticks 2523204701000 # Number of ticks simulated
-final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.526170 # Number of seconds simulated
+sim_ticks 2526169857500 # Number of ticks simulated
+final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55288 # Simulator instruction rate (inst/s)
-host_op_rate 71140 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2313219719 # Simulator tick rate (ticks/s)
-host_mem_usage 409988 # Number of bytes of host memory used
-host_seconds 1090.78 # Real time elapsed on the host
-sim_insts 60306320 # Number of instructions simulated
-sim_ops 77597310 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 46796 # Simulator instruction rate (inst/s)
+host_op_rate 60213 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1960134913 # Simulator tick rate (ticks/s)
+host_mem_usage 468616 # Number of bytes of host memory used
+host_seconds 1288.77 # Real time elapsed on the host
+sim_insts 60309637 # Number of instructions simulated
+sim_ops 77601213 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096856 # Total number of read requests seen
-system.physmem.writeReqs 813138 # Total number of write requests seen
-system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966198784 # Total number of bytes read from memory
-system.physmem.bytesWritten 52040832 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2523203522000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 36 # Categorize read packet sizes
-system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154612 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1943854 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59120 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
+system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096868 # Number of read requests accepted
+system.physmem.writeReqs 813159 # Number of write requests accepted
+system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 943297 # Per bank write bursts
+system.physmem.perBankRdBursts::1 937033 # Per bank write bursts
+system.physmem.perBankRdBursts::2 936962 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 942693 # Per bank write bursts
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+system.physmem.perBankWrBursts::3 6552 # Per bank write bursts
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+system.physmem.perBankWrBursts::5 6711 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6720 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6668 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7045 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6826 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6497 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6136 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7072 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6672 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6956 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6819 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 2526168741500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 38 # Read request sizes (log2)
+system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 154622 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
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+system.physmem.writePktSize::2 754018 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
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+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 59141 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests
-system.physmem.totBusLat 60386192000 # Total cycles spent in databus access
-system.physmem.totBankLat 16356620000 # Total cycles spent in bank access
-system.physmem.avgQLat 21743.10 # Average queueing delay per request
-system.physmem.avgBankLat 1083.47 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26826.57 # Average memory access latency
-system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.52 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.16 # Average read queue length over time
-system.physmem.avgWrQLen 10.68 # Average write queue length over time
-system.physmem.readRowHits 15052450 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784654 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes
-system.physmem.avgGap 158592.36 # Average gap between requests
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads
+system.physmem.totQLat 571195583500 # Total ticks spent queuing
+system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks
+system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 2.99 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 14041195 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91389 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes
+system.physmem.avgGap 158778.41 # Average gap between requests
+system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54878638 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16149508 # Transaction distribution
+system.membus.trans_dist::ReadResp 16149508 # Transaction distribution
+system.membus.trans_dist::WriteReq 763349 # Transaction distribution
+system.membus.trans_dist::WriteResp 763349 # Transaction distribution
+system.membus.trans_dist::Writeback 59141 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138632762 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.iobus.throughput 48266001 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121928118 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 14755327 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions.
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14986991 # DTB read hits
-system.cpu.checker.dtb.read_misses 7307 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227488 # DTB write hits
-system.cpu.checker.dtb.write_misses 2189 # DTB write misses
+system.cpu.checker.dtb.read_hits 14987589 # DTB read hits
+system.cpu.checker.dtb.read_misses 7306 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227681 # DTB write hits
+system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994298 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229677 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994895 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229872 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26214479 # DTB hits
-system.cpu.checker.dtb.misses 9496 # DTB misses
-system.cpu.checker.dtb.accesses 26223975 # DTB accesses
-system.cpu.checker.itb.inst_hits 61480313 # ITB inst hits
-system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
+system.cpu.checker.dtb.hits 26215270 # DTB hits
+system.cpu.checker.dtb.misses 9497 # DTB misses
+system.cpu.checker.dtb.accesses 26224767 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.inst_hits 61483612 # ITB inst hits
+system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61484784 # ITB inst accesses
-system.cpu.checker.itb.hits 61480313 # DTB hits
-system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61484784 # DTB accesses
-system.cpu.checker.numCycles 77883110 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 61488085 # ITB inst accesses
+system.cpu.checker.itb.hits 61483612 # DTB hits
+system.cpu.checker.itb.misses 4473 # DTB misses
+system.cpu.checker.itb.accesses 61488085 # DTB accesses
+system.cpu.checker.numCycles 77887007 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51212683 # DTB read hits
-system.cpu.dtb.read_misses 73387 # DTB read misses
-system.cpu.dtb.write_hits 11701466 # DTB write hits
-system.cpu.dtb.write_misses 17011 # DTB write misses
+system.cpu.dtb.read_hits 51187284 # DTB read hits
+system.cpu.dtb.read_misses 65383 # DTB read misses
+system.cpu.dtb.write_hits 11703682 # DTB write hits
+system.cpu.dtb.write_misses 15916 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7759 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51286070 # DTB read accesses
-system.cpu.dtb.write_accesses 11718477 # DTB write accesses
+system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51252667 # DTB read accesses
+system.cpu.dtb.write_accesses 11719598 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 62914149 # DTB hits
-system.cpu.dtb.misses 90398 # DTB misses
-system.cpu.dtb.accesses 63004547 # DTB accesses
-system.cpu.itb.inst_hits 11530598 # ITB inst hits
-system.cpu.itb.inst_misses 11503 # ITB inst misses
+system.cpu.dtb.hits 62890966 # DTB hits
+system.cpu.dtb.misses 81299 # DTB misses
+system.cpu.dtb.accesses 62972265 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 11527099 # ITB inst hits
+system.cpu.itb.inst_misses 11249 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5166 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 11542101 # ITB inst accesses
-system.cpu.itb.hits 11530598 # DTB hits
-system.cpu.itb.misses 11503 # DTB misses
-system.cpu.itb.accesses 11542101 # DTB accesses
-system.cpu.numCycles 469830472 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 11538348 # ITB inst accesses
+system.cpu.itb.hits 11527099 # DTB hits
+system.cpu.itb.misses 11249 # DTB misses
+system.cpu.itb.accesses 11538348 # DTB accesses
+system.cpu.numCycles 477119451 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued
-system.cpu.iq.rate 0.261848 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued
+system.cpu.iq.rate 0.257655 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221038 # number of nop insts executed
-system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11477980 # Number of branches executed
-system.cpu.iew.exec_stores 12213052 # Number of stores executed
-system.cpu.iew.exec_rate 0.257448 # Inst execution rate
-system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47051195 # num instructions producing a value
-system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value
+system.cpu.iew.exec_nop 221278 # number of nop insts executed
+system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11821235 # Number of branches executed
+system.cpu.iew.exec_stores 12215513 # Number of stores executed
+system.cpu.iew.exec_rate 0.253301 # Inst execution rate
+system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47029089 # num instructions producing a value
+system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60456701 # Number of instructions committed
-system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60460018 # Number of instructions committed
+system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27385892 # Number of memory references committed
-system.cpu.commit.loads 15654083 # Number of loads committed
-system.cpu.commit.membars 403583 # Number of memory barriers committed
-system.cpu.commit.branches 9961154 # Number of branches committed
+system.cpu.commit.refs 27386851 # Number of memory references committed
+system.cpu.commit.loads 15654790 # Number of loads committed
+system.cpu.commit.membars 403577 # Number of memory barriers committed
+system.cpu.commit.branches 10306380 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68853054 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991222 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 69191623 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991253 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 238273902 # The number of ROB reads
-system.cpu.rob.rob_writes 196332947 # The number of ROB writes
-system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60306320 # Number of Instructions Simulated
-system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated
-system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 547824488 # number of integer regfile reads
-system.cpu.int_regfile_writes 87698032 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8340 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831851 # number of misc regfile writes
-system.cpu.icache.replacements 979772 # number of replacements
-system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use
-system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits
-system.cpu.icache.overall_hits::total 10466836 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses
-system.cpu.icache.overall_misses::total 1059904 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 242979782 # The number of ROB reads
+system.cpu.rob.rob_writes 196005989 # The number of ROB writes
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+system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 607596 # number of writebacks
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+system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs nan # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements 0 # number of replacements
+system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses 0 # Number of tag accesses
+system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff