---------- Begin Simulation Statistics ----------
-sim_seconds 1.102958 # Number of seconds simulated
-sim_ticks 1102958416500 # Number of ticks simulated
-final_tick 1102958416500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.102954 # Number of seconds simulated
+sim_ticks 1102954033500 # Number of ticks simulated
+final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66795 # Simulator instruction rate (inst/s)
-host_op_rate 85978 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1196309321 # Simulator tick rate (ticks/s)
-host_mem_usage 404244 # Number of bytes of host memory used
-host_seconds 921.97 # Real time elapsed on the host
-sim_insts 61582525 # Number of instructions simulated
-sim_ops 79269125 # Number of ops (including micro ops) simulated
+host_inst_rate 66183 # Simulator instruction rate (inst/s)
+host_op_rate 85190 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1185337549 # Simulator tick rate (ticks/s)
+host_mem_usage 402972 # Number of bytes of host memory used
+host_seconds 930.50 # Real time elapsed on the host
+sim_insts 61582952 # Number of instructions simulated
+sim_ops 79269552 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 410752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4380596 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 405056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5224880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59182180 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 410752 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 405056 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 815808 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4259968 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory
+system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 404608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 814720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4260416 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7287312 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7287760 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6418 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68519 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6329 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81665 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6257812 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66562 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6408 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68518 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6322 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 81683 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6257809 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66569 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823398 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 44207273 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 823405 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 44207449 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 372409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3971678 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 367245 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4737150 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53657671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 372409 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 367245 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 739654 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3862311 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 928 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 53657710 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 366840 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3862732 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2729336 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6607060 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3862311 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 44207273 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6607492 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3862732 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 372409 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3987091 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 367245 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7466486 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 60264731 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257812 # Total number of read requests seen
-system.physmem.writeReqs 823398 # Total number of write requests seen
-system.physmem.cpureqs 242000 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 400499968 # Total number of bytes read from memory
-system.physmem.bytesWritten 52697472 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59182180 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7287312 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12579 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 391407 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 390854 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 391610 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391518 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 390872 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 390926 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 390705 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390857 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 391233 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 390526 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 390472 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 391263 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51413 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 51006 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51680 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51540 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50963 # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6257809 # Total number of read requests seen
+system.physmem.writeReqs 823405 # Total number of write requests seen
+system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 400499776 # Total number of bytes read from memory
+system.physmem.bytesWritten 52697920 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 391396 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::2 390867 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51665 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51495 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51885 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51842 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51173 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32627 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1102957282500 # Total gap between requests
+system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1102952897500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 162859 # Categorize read packet sizes
+system.physmem.readPktSize::6 162856 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 756836 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 66562 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 493912 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 430569 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 145 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 66569 # Categorize write packet sizes
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3002 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::6 3115 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::8 3157 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32902 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32846 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32798 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32756 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32735 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32643 # What write queue length does an incoming req see
-system.physmem.totQLat 199244474250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 239068869250 # Sum of mem lat for all requests
-system.physmem.totBusLat 31288670000 # Total cycles spent in databus access
-system.physmem.totBankLat 8535725000 # Total cycles spent in bank access
-system.physmem.avgQLat 31839.72 # Average queueing delay per request
-system.physmem.avgBankLat 1364.03 # Average bank access latency per request
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system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50778.834905 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 46739.928982 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.507489 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10156.562681 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10098.960918 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.088924 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.694712 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10077.604541 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37457.263254 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41132.477559 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 39466.861514 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44454.161725 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50145.589408 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 46316.033088 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.000583 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10167.910124 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10103.974474 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.495370 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.055288 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10061.593985 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37401.096989 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41147.448442 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39449.774697 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 5991996 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4570590 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 295222 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3736406 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2908427 # Number of BTB hits
+system.cpu0.branchPred.lookups 5994746 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.840229 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 670993 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28752 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8901229 # DTB read hits
-system.cpu0.dtb.read_misses 28750 # DTB read misses
-system.cpu0.dtb.write_hits 5135502 # DTB write hits
-system.cpu0.dtb.write_misses 5613 # DTB write misses
+system.cpu0.dtb.read_hits 8900432 # DTB read hits
+system.cpu0.dtb.read_misses 28720 # DTB read misses
+system.cpu0.dtb.write_hits 5136537 # DTB write hits
+system.cpu0.dtb.write_misses 5640 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1817 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 968 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 548 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8929979 # DTB read accesses
-system.cpu0.dtb.write_accesses 5141115 # DTB write accesses
+system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8929152 # DTB read accesses
+system.cpu0.dtb.write_accesses 5142177 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14036731 # DTB hits
-system.cpu0.dtb.misses 34363 # DTB misses
-system.cpu0.dtb.accesses 14071094 # DTB accesses
-system.cpu0.itb.inst_hits 4213364 # ITB inst hits
-system.cpu0.itb.inst_misses 5048 # ITB inst misses
+system.cpu0.dtb.hits 14036969 # DTB hits
+system.cpu0.dtb.misses 34360 # DTB misses
+system.cpu0.dtb.accesses 14071329 # DTB accesses
+system.cpu0.itb.inst_hits 4213831 # ITB inst hits
+system.cpu0.itb.inst_misses 5055 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1344 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4218412 # ITB inst accesses
-system.cpu0.itb.hits 4213364 # DTB hits
-system.cpu0.itb.misses 5048 # DTB misses
-system.cpu0.itb.accesses 4218412 # DTB accesses
-system.cpu0.numCycles 67828518 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses
+system.cpu0.itb.hits 4213831 # DTB hits
+system.cpu0.itb.misses 5055 # DTB misses
+system.cpu0.itb.accesses 4218886 # DTB accesses
+system.cpu0.numCycles 67827180 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11769514 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 31989018 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 5991996 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3579420 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7508503 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1450801 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 60684 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 20631180 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 48154 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 85409 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4211784 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 156653 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2012 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41149957 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.004329 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.384713 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33648798 81.77% 81.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 562155 1.37% 83.14% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 818096 1.99% 85.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 677471 1.65% 86.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 773499 1.88% 88.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 558438 1.36% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 664363 1.61% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 352105 0.86% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3095032 7.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41149957 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088340 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.471616 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12268271 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20578267 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6812810 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 512754 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 977855 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 934513 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64660 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 39970940 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 212731 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 977855 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12837244 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5740254 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12723807 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6707246 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2163551 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38872652 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1850 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 437651 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1233683 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39221318 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175562913 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175528548 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34365 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30916412 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8304905 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 410995 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 369967 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5350401 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7642102 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5682819 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1122438 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1201311 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36799804 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 894837 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37219527 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 80251 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6274775 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13129416 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 256270 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41149957 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.904485 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.513383 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 26028016 63.25% 63.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5729313 13.92% 77.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3155280 7.67% 84.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2465546 5.99% 90.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2105206 5.12% 95.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 932712 2.27% 98.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 494007 1.20% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 184426 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 55451 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41149957 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 26761 2.50% 2.50% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 453 0.04% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 841654 78.63% 81.17% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 201534 18.83% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22319985 59.97% 60.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46930 0.13% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9357970 25.14% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5441771 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37219527 # Type of FU issued
-system.cpu0.iq.rate 0.548730 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070402 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028759 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 116765436 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 43977253 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34319519 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8378 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4660 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38233387 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4393 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 306639 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued
+system.cpu0.iq.rate 0.548786 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1370211 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2367 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13030 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 536244 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192745 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5335 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 977855 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4123044 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 98683 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37812695 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 84467 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7642102 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5682819 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571073 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 39963 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2983 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13030 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 149756 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 117796 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 267552 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36844879 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9216416 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 374648 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118054 # number of nop insts executed
-system.cpu0.iew.exec_refs 14611375 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4852197 # Number of branches executed
-system.cpu0.iew.exec_stores 5394959 # Number of stores executed
-system.cpu0.iew.exec_rate 0.543206 # Inst execution rate
-system.cpu0.iew.wb_sent 36651456 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34323388 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18278983 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35164474 # num instructions consuming a value
+system.cpu0.iew.exec_nop 117682 # number of nop insts executed
+system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4852307 # Number of branches executed
+system.cpu0.iew.exec_stores 5396032 # Number of stores executed
+system.cpu0.iew.exec_rate 0.543238 # Inst execution rate
+system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18280728 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.506032 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.519814 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6082175 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 231668 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40172102 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.778393 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.739779 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28502177 70.95% 70.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5716215 14.23% 85.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1915316 4.77% 89.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 977454 2.43% 92.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 784200 1.95% 94.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 521856 1.30% 95.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 386686 0.96% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 221286 0.55% 97.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1146912 2.85% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle
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system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu0.commit.membars 229601 # Number of memory barriers committed
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system.cpu0.commit.function_calls 489162 # Number of function calls committed.
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.quiesceCycles 2138046604 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23589916 # Number of Instructions Simulated
-system.cpu0.committedOps 31188961 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23589916 # Number of Instructions Simulated
-system.cpu0.cpi 2.875318 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.875318 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.347788 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.347788 # IPC: Total IPC of All Threads
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+system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated
+system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads
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+system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads
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system.cpu0.fp_regfile_writes 898 # number of floating regfile writes
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system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.occ_percent::total 0.998068 # Average percentage of cache occupancy
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.784602 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency
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-system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 183 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.icache.demand_mshr_miss_latency::total 4741290497 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu0.dcache.LoadLockedReq_hits::total 139041 # number of LoadLockedReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::total 8784 # number of LoadLockedReq misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4050141991 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66675500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66675500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31721000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31721000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6421801991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6421801991 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6421801991 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6421801991 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513534500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513534500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180320378 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180320378 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693854878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693854878 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030595 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030595 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027472 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027472 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056183 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056183 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051739 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051739 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029238 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029238 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8023.525872 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8023.525872 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4242.476929 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4242.476929 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9066051 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7453207 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 407044 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6058627 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5236584 # Number of BTB hits
+system.cpu1.branchPred.lookups 9076266 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 86.431860 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 771955 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 42437 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42902362 # DTB read hits
-system.cpu1.dtb.read_misses 36935 # DTB read misses
-system.cpu1.dtb.write_hits 6824519 # DTB write hits
-system.cpu1.dtb.write_misses 10718 # DTB write misses
+system.cpu1.dtb.read_hits 42903620 # DTB read hits
+system.cpu1.dtb.read_misses 37068 # DTB read misses
+system.cpu1.dtb.write_hits 6823215 # DTB write hits
+system.cpu1.dtb.write_misses 10679 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2714 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 645 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42939297 # DTB read accesses
-system.cpu1.dtb.write_accesses 6835237 # DTB write accesses
+system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42940688 # DTB read accesses
+system.cpu1.dtb.write_accesses 6833894 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49726881 # DTB hits
-system.cpu1.dtb.misses 47653 # DTB misses
-system.cpu1.dtb.accesses 49774534 # DTB accesses
-system.cpu1.itb.inst_hits 8392998 # ITB inst hits
-system.cpu1.itb.inst_misses 5431 # ITB inst misses
+system.cpu1.dtb.hits 49726835 # DTB hits
+system.cpu1.dtb.misses 47747 # DTB misses
+system.cpu1.dtb.accesses 49774582 # DTB accesses
+system.cpu1.itb.inst_hits 8394995 # ITB inst hits
+system.cpu1.itb.inst_misses 5378 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8398429 # ITB inst accesses
-system.cpu1.itb.hits 8392998 # DTB hits
-system.cpu1.itb.misses 5431 # DTB misses
-system.cpu1.itb.accesses 8398429 # DTB accesses
-system.cpu1.numCycles 408779942 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses
+system.cpu1.itb.hits 8394995 # DTB hits
+system.cpu1.itb.misses 5378 # DTB misses
+system.cpu1.itb.accesses 8400373 # DTB accesses
+system.cpu1.numCycles 408777731 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19814855 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 66055643 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9066051 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6008539 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14146730 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3957386 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 64683 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77267641 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42583 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 129813 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8391200 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 740435 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2770 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 114169430 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.700459 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.044215 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100030180 87.62% 87.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 795116 0.70% 88.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 937715 0.82% 89.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1888304 1.65% 90.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1526967 1.34% 92.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 578073 0.51% 92.63% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2128721 1.86% 94.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 409818 0.36% 94.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5874536 5.15% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 114169430 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022178 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.161592 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21335636 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 76916914 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12791603 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 523584 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2601693 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1104215 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 98013 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 75225150 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 326089 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2601693 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22720139 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 31942959 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40740266 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11835652 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4328721 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69758398 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 18799 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 669077 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3086745 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 378 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73725482 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 321189458 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 321130296 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59162 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49052273 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24673209 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 444958 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 387932 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7868643 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13207791 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8146456 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1036357 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1539549 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63487430 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1157915 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89117422 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 94398 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16230957 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45692140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 277223 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 114169430 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.780572 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.518996 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83779617 73.38% 73.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8401659 7.36% 80.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4300327 3.77% 84.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3769049 3.30% 87.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10578609 9.27% 97.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1966316 1.72% 98.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1028949 0.90% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 270980 0.24% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 73924 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 114169430 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 31906 0.41% 0.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7548325 95.86% 96.28% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 292902 3.72% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37601994 42.19% 42.55% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59184 0.07% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43968762 49.34% 91.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7172015 8.05% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89117422 # Type of FU issued
-system.cpu1.iq.rate 0.218008 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7874129 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088357 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300405264 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80884614 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53615647 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 15005 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6847 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96669700 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7919 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 342898 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued
+system.cpu1.iq.rate 0.218050 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3454228 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 16932 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1307521 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31906117 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 888056 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2601693 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24180087 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 359608 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64749015 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 111417 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13207791 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8146456 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 869148 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64619 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3744 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 16932 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 200731 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 155107 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 355838 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86675355 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43272699 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2442067 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 103670 # number of nop insts executed
-system.cpu1.iew.exec_refs 50383092 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6989591 # Number of branches executed
-system.cpu1.iew.exec_stores 7110393 # Number of stores executed
-system.cpu1.iew.exec_rate 0.212034 # Inst execution rate
-system.cpu1.iew.wb_sent 85698110 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53622494 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29929482 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53410166 # num instructions consuming a value
+system.cpu1.iew.exec_nop 104622 # number of nop insts executed
+system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 6997981 # Number of branches executed
+system.cpu1.iew.exec_stores 7109203 # Number of stores executed
+system.cpu1.iew.exec_rate 0.212104 # Inst execution rate
+system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29926721 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131177 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560371 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 16109317 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880692 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 310619 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111567737 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.431575 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.399552 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94819418 84.99% 84.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8239382 7.39% 92.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2114964 1.90% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1255344 1.13% 95.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1246323 1.12% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 567268 0.51% 97.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1001355 0.90% 97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 504765 0.45% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1818918 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111567737 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38062248 # Number of instructions committed
-system.cpu1.commit.committedOps 48149803 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38062798 # Number of instructions committed
+system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16592498 # Number of memory references committed
-system.cpu1.commit.loads 9753563 # Number of loads committed
+system.cpu1.commit.refs 16592681 # Number of memory references committed
+system.cpu1.commit.loads 9753740 # Number of loads committed
system.cpu1.commit.membars 190132 # Number of memory barriers committed
-system.cpu1.commit.branches 5967184 # Number of branches committed
+system.cpu1.commit.branches 5967363 # Number of branches committed
system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42685255 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions.
system.cpu1.commit.function_calls 534609 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1818918 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 172963873 # The number of ROB reads
-system.cpu1.rob.rob_writes 131212452 # The number of ROB writes
-system.cpu1.timesIdled 1408163 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026210 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026210 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112247 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112247 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100539 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100539 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027064 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027064 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7156.996723 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7156.996723 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3079.490806 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3079.490806 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540179772418 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 540179772418 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540179772418 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 540179772418 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41712 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff