---------- Begin Simulation Statistics ----------
-sim_seconds 47.535940 # Number of seconds simulated
-sim_ticks 47535940136000 # Number of ticks simulated
-final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.310816 # Number of seconds simulated
+sim_ticks 47310816168000 # Number of ticks simulated
+final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 200561 # Simulator instruction rate (inst/s)
-host_op_rate 235891 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10615931561 # Simulator tick rate (ticks/s)
-host_mem_usage 769436 # Number of bytes of host memory used
-host_seconds 4477.79 # Real time elapsed on the host
-sim_insts 898069628 # Number of instructions simulated
-sim_ops 1056270581 # Number of ops (including micro ops) simulated
+host_inst_rate 279196 # Simulator instruction rate (inst/s)
+host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
+host_mem_usage 770320 # Number of bytes of host memory used
+host_seconds 2980.95 # Real time elapsed on the host
+sim_insts 832269934 # Number of instructions simulated
+sim_ops 991180133 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
+system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 986704 # Number of read requests accepted
-system.physmem.writeReqs 1185440 # Number of write requests accepted
-system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue
-system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1084146 # Number of read requests accepted
+system.physmem.writeReqs 1315173 # Number of write requests accepted
+system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
+system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 63842 # Per bank write bursts
-system.physmem.perBankRdBursts::1 66317 # Per bank write bursts
-system.physmem.perBankRdBursts::2 58522 # Per bank write bursts
-system.physmem.perBankRdBursts::3 64863 # Per bank write bursts
-system.physmem.perBankRdBursts::4 59095 # Per bank write bursts
-system.physmem.perBankRdBursts::5 67998 # Per bank write bursts
-system.physmem.perBankRdBursts::6 58322 # Per bank write bursts
-system.physmem.perBankRdBursts::7 56006 # Per bank write bursts
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-system.physmem.perBankRdBursts::9 111449 # Per bank write bursts
-system.physmem.perBankRdBursts::10 50777 # Per bank write bursts
-system.physmem.perBankRdBursts::11 58061 # Per bank write bursts
-system.physmem.perBankRdBursts::12 51458 # Per bank write bursts
-system.physmem.perBankRdBursts::13 52890 # Per bank write bursts
-system.physmem.perBankRdBursts::14 54883 # Per bank write bursts
-system.physmem.perBankRdBursts::15 59208 # Per bank write bursts
-system.physmem.perBankWrBursts::0 77123 # Per bank write bursts
-system.physmem.perBankWrBursts::1 81948 # Per bank write bursts
-system.physmem.perBankWrBursts::2 74623 # Per bank write bursts
-system.physmem.perBankWrBursts::3 80009 # Per bank write bursts
-system.physmem.perBankWrBursts::4 75007 # Per bank write bursts
-system.physmem.perBankWrBursts::5 80611 # Per bank write bursts
-system.physmem.perBankWrBursts::6 72005 # Per bank write bursts
-system.physmem.perBankWrBursts::7 72012 # Per bank write bursts
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-system.physmem.perBankWrBursts::9 73887 # Per bank write bursts
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-system.physmem.perBankWrBursts::12 68786 # Per bank write bursts
-system.physmem.perBankWrBursts::13 69993 # Per bank write bursts
-system.physmem.perBankWrBursts::14 72865 # Per bank write bursts
-system.physmem.perBankWrBursts::15 75967 # Per bank write bursts
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+system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 44 # Number of times write queue was full causing retry
-system.physmem.totGap 47535938023500 # Total gap between requests
+system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
+system.physmem.totGap 47310814104000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 986674 # Read request sizes (log2)
+system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1182866 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads
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-system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers
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+system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
+system.physmem.totQLat 57570179828 # Total ticks spent queuing
+system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing
-system.physmem.readRowHits 734466 # Number of row buffer hits during reads
-system.physmem.writeRowHits 450279 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes
-system.physmem.avgGap 21884340.09 # Average gap between requests
-system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.717535 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.677991 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
+system.physmem.readRowHits 798943 # Number of row buffer hits during reads
+system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
+system.physmem.avgGap 19718434.32 # Average gap between requests
+system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
+system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
+system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
+system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
+system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
+system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 146462396 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches.
+system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 302048 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 94909868 # DTB read hits
-system.cpu0.dtb.read_misses 253021 # DTB read misses
-system.cpu0.dtb.write_hits 83284387 # DTB write hits
-system.cpu0.dtb.write_misses 49027 # DTB write misses
+system.cpu0.dtb.read_hits 91107490 # DTB read hits
+system.cpu0.dtb.read_misses 238663 # DTB read misses
+system.cpu0.dtb.write_hits 81148084 # DTB write hits
+system.cpu0.dtb.write_misses 53270 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 95162889 # DTB read accesses
-system.cpu0.dtb.write_accesses 83333414 # DTB write accesses
+system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
+system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 178194255 # DTB hits
-system.cpu0.dtb.misses 302048 # DTB misses
-system.cpu0.dtb.accesses 178496303 # DTB accesses
+system.cpu0.dtb.hits 172255574 # DTB hits
+system.cpu0.dtb.misses 291933 # DTB misses
+system.cpu0.dtb.accesses 172547507 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 66529 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks 65131 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 260612167 # ITB inst hits
-system.cpu0.itb.inst_misses 66529 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 201165320 # ITB inst hits
+system.cpu0.itb.inst_misses 65131 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses
-system.cpu0.itb.hits 260612167 # DTB hits
-system.cpu0.itb.misses 66529 # DTB misses
-system.cpu0.itb.accesses 260678696 # DTB accesses
-system.cpu0.numCycles 1099930824 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
+system.cpu0.itb.hits 201165320 # DTB hits
+system.cpu0.itb.misses 65131 # DTB misses
+system.cpu0.itb.accesses 201230451 # DTB accesses
+system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 923231946 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 487305462 # Number of instructions committed
-system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.257169 # CPI: cycles per instruction
-system.cpu0.ipc 0.443033 # IPC: instructions per cycle
+system.cpu0.committedInsts 433947137 # Number of instructions committed
+system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.127522 # CPI: cycles per instruction
+system.cpu0.ipc 0.470030 # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
-system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction
-system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction
-system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction
-system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction
-system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction
-system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
+system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
+system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
+system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.op_class_0::total 572197777 # Class of committed instruction
+system.cpu0.op_class_0::total 516803462 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed
-system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 5972011 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
+system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements 6005277 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits
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-system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits
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-system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses
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-system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses
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-system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses
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-system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses
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-system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles
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-system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency
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-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses
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-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.replacements 10516028 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor
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-system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses
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-system.cpu0.icache.overall_accesses::total 260427816 # number of overall (read+write) accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency
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+system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses
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system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id
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+system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 127453033 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits
+system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches.
+system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 261031 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 80497438 # DTB read hits
-system.cpu1.dtb.read_misses 213464 # DTB read misses
-system.cpu1.dtb.write_hits 70911031 # DTB write hits
-system.cpu1.dtb.write_misses 47567 # DTB write misses
+system.cpu1.dtb.read_hits 85144665 # DTB read hits
+system.cpu1.dtb.read_misses 232605 # DTB read misses
+system.cpu1.dtb.write_hits 73861979 # DTB write hits
+system.cpu1.dtb.write_misses 45370 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 80710902 # DTB read accesses
-system.cpu1.dtb.write_accesses 70958598 # DTB write accesses
+system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
+system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 151408469 # DTB hits
-system.cpu1.dtb.misses 261031 # DTB misses
-system.cpu1.dtb.accesses 151669500 # DTB accesses
+system.cpu1.dtb.hits 159006644 # DTB hits
+system.cpu1.dtb.misses 277975 # DTB misses
+system.cpu1.dtb.accesses 159284619 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 64962 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks 63204 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 225980528 # ITB inst hits
-system.cpu1.itb.inst_misses 64962 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 184175570 # ITB inst hits
+system.cpu1.itb.inst_misses 63204 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses
-system.cpu1.itb.hits 225980528 # DTB hits
-system.cpu1.itb.misses 64962 # DTB misses
-system.cpu1.itb.accesses 226045490 # DTB accesses
-system.cpu1.numCycles 884296043 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
+system.cpu1.itb.hits 184175570 # DTB hits
+system.cpu1.itb.misses 63204 # DTB misses
+system.cpu1.itb.accesses 184238774 # DTB accesses
+system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 798693745 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 410764166 # Number of instructions committed
-system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.152807 # CPI: cycles per instruction
-system.cpu1.ipc 0.464510 # IPC: instructions per cycle
+system.cpu1.committedInsts 398322797 # Number of instructions committed
+system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.005142 # CPI: cycles per instruction
+system.cpu1.ipc 0.498718 # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction
-system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction
-system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction
-system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction
-system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
+system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
+system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.op_class_0::total 484072804 # Class of committed instruction
+system.cpu1.op_class_0::total 474376671 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed
-system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 5011869 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
+system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements 5132038 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits
-system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses
-system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses
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-system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles
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-system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles
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-system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses)
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-system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
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+system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses)
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks
-system.cpu1.dcache.writebacks::total 5011891 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits
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-system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits
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-system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses
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-system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency
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-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency
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-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency
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-system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
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-system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_miss_rate::total 0.037423 # miss rate for ReadReq accesses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency
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+system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses
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+system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles
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system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
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-system.cpu1.l2cache.WritebackDirty_hits::total 3161302 # number of WritebackDirty hits
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+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.237116 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.237116 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080624 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268190 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268190 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.603347 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.603347 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139346 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40390 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40390 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136973 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136973 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115843 # number of replacements
-system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements 115597 # number of replacements
+system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1043106 # Number of tag accesses
-system.iocache.tags.data_accesses 1043106 # Number of data accesses
+system.iocache.tags.tag_accesses 1040910 # Number of tag accesses
+system.iocache.tags.data_accesses 1040910 # Number of data accesses
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system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115901 # number of demand (read+write) misses
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+system.iocache.demand_misses::total 115657 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115861 # number of overall misses
-system.iocache.overall_misses::total 115901 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles
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+system.iocache.overall_misses::total 115657 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
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+system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses
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+system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency
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+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq 42476 # Transaction distribution
+system.membus.trans_dist::ReadResp 989688 # Transaction distribution
+system.membus.trans_dist::WriteReq 37999 # Transaction distribution
+system.membus.trans_dist::WriteResp 37999 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution
+system.membus.trans_dist::CleanEvict 291937 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 143483 # Transaction distribution
-system.membus.trans_dist::ReadExResp 126149 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 621301 # Total snoops (count)
-system.membus.snoop_fanout::samples 3957559 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.trans_dist::ReadExReq 150791 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135122 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution
+system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 586564 # Total snoops (count)
+system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
+system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3957559 # Request fanout histogram
-system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2402773 # Request fanout histogram
+system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3080857 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3035429 # Total snoops (count)
+system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff