---------- Begin Simulation Statistics ----------
-sim_seconds 47.349389 # Number of seconds simulated
-sim_ticks 47349388766500 # Number of ticks simulated
-final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.310816 # Number of seconds simulated
+sim_ticks 47310816168000 # Number of ticks simulated
+final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 148460 # Simulator instruction rate (inst/s)
-host_op_rate 174619 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7799944718 # Simulator tick rate (ticks/s)
-host_mem_usage 883812 # Number of bytes of host memory used
-host_seconds 6070.48 # Real time elapsed on the host
-sim_insts 901223526 # Number of instructions simulated
-sim_ops 1060022042 # Number of ops (including micro ops) simulated
+host_inst_rate 279196 # Simulator instruction rate (inst/s)
+host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
+host_mem_usage 770320 # Number of bytes of host memory used
+host_seconds 2980.95 # Real time elapsed on the host
+sim_insts 832269934 # Number of instructions simulated
+sim_ops 991180133 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory
-system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1817460 # Number of read requests accepted
-system.physmem.writeReqs 1459105 # Number of write requests accepted
-system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue
-system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 109521 # Per bank write bursts
-system.physmem.perBankRdBursts::1 125500 # Per bank write bursts
-system.physmem.perBankRdBursts::2 109858 # Per bank write bursts
-system.physmem.perBankRdBursts::3 118807 # Per bank write bursts
-system.physmem.perBankRdBursts::4 114750 # Per bank write bursts
-system.physmem.perBankRdBursts::5 133958 # Per bank write bursts
-system.physmem.perBankRdBursts::6 108183 # Per bank write bursts
-system.physmem.perBankRdBursts::7 109296 # Per bank write bursts
-system.physmem.perBankRdBursts::8 104951 # Per bank write bursts
-system.physmem.perBankRdBursts::9 157608 # Per bank write bursts
-system.physmem.perBankRdBursts::10 96466 # Per bank write bursts
-system.physmem.perBankRdBursts::11 111139 # Per bank write bursts
-system.physmem.perBankRdBursts::12 103753 # Per bank write bursts
-system.physmem.perBankRdBursts::13 116262 # Per bank write bursts
-system.physmem.perBankRdBursts::14 95073 # Per bank write bursts
-system.physmem.perBankRdBursts::15 101437 # Per bank write bursts
-system.physmem.perBankWrBursts::0 88391 # Per bank write bursts
-system.physmem.perBankWrBursts::1 94888 # Per bank write bursts
-system.physmem.perBankWrBursts::2 89089 # Per bank write bursts
-system.physmem.perBankWrBursts::3 94540 # Per bank write bursts
-system.physmem.perBankWrBursts::4 92096 # Per bank write bursts
-system.physmem.perBankWrBursts::5 104028 # Per bank write bursts
-system.physmem.perBankWrBursts::6 87215 # Per bank write bursts
-system.physmem.perBankWrBursts::7 89925 # Per bank write bursts
-system.physmem.perBankWrBursts::8 85891 # Per bank write bursts
-system.physmem.perBankWrBursts::9 90043 # Per bank write bursts
-system.physmem.perBankWrBursts::10 85085 # Per bank write bursts
-system.physmem.perBankWrBursts::11 94536 # Per bank write bursts
-system.physmem.perBankWrBursts::12 86659 # Per bank write bursts
-system.physmem.perBankWrBursts::13 94890 # Per bank write bursts
-system.physmem.perBankWrBursts::14 85144 # Per bank write bursts
-system.physmem.perBankWrBursts::15 88902 # Per bank write bursts
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
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+system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
+system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
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+system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
+system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
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+system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
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+system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1084146 # Number of read requests accepted
+system.physmem.writeReqs 1315173 # Number of write requests accepted
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+system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
+system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 69238 # Per bank write bursts
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+system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 47349386828500 # Total gap between requests
+system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
+system.physmem.totGap 47310814104000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1817418 # Read request sizes (log2)
+system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
-system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1456502 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads
-system.physmem.totQLat 101322311265 # Total ticks spent queuing
-system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst
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+system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
+system.physmem.totQLat 57570179828 # Total ticks spent queuing
+system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing
-system.physmem.readRowHits 1479200 # Number of row buffer hits during reads
-system.physmem.writeRowHits 893785 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes
-system.physmem.avgGap 14450922.48 # Average gap between requests
-system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states
-system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.790877 # Core power per rank (mW)
-system.physmem.averagePower::1 668.736116 # Core power per rank (mW)
-system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
+system.physmem.readRowHits 798943 # Number of row buffer hits during reads
+system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
+system.physmem.avgGap 19718434.32 # Average gap between requests
+system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
+system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
+system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
+system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
+system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
+system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 127854962 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits
+system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 80634882 # DTB read hits
-system.cpu0.dtb.read_misses 217470 # DTB read misses
-system.cpu0.dtb.write_hits 71942682 # DTB write hits
-system.cpu0.dtb.write_misses 47848 # DTB write misses
+system.cpu0.dtb.read_hits 91107490 # DTB read hits
+system.cpu0.dtb.read_misses 238663 # DTB read misses
+system.cpu0.dtb.write_hits 81148084 # DTB write hits
+system.cpu0.dtb.write_misses 53270 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 80852352 # DTB read accesses
-system.cpu0.dtb.write_accesses 71990530 # DTB write accesses
+system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
+system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 152577564 # DTB hits
-system.cpu0.dtb.misses 265318 # DTB misses
-system.cpu0.dtb.accesses 152842882 # DTB accesses
+system.cpu0.dtb.hits 172255574 # DTB hits
+system.cpu0.dtb.misses 291933 # DTB misses
+system.cpu0.dtb.accesses 172547507 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 228743332 # ITB inst hits
-system.cpu0.itb.inst_misses 63317 # ITB inst misses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks 65131 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 201165320 # ITB inst hits
+system.cpu0.itb.inst_misses 65131 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses
-system.cpu0.itb.hits 228743332 # DTB hits
-system.cpu0.itb.misses 63317 # DTB misses
-system.cpu0.itb.accesses 228806649 # DTB accesses
-system.cpu0.numCycles 867293351 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
+system.cpu0.itb.hits 201165320 # DTB hits
+system.cpu0.itb.misses 65131 # DTB misses
+system.cpu0.itb.accesses 201230451 # DTB accesses
+system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 923231946 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 417325536 # Number of instructions committed
-system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.078218 # CPI: cycles per instruction
-system.cpu0.ipc 0.481182 # IPC: instructions per cycle
+system.cpu0.committedInsts 433947137 # Number of instructions committed
+system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.127522 # CPI: cycles per instruction
+system.cpu0.ipc 0.470030 # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
+system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
+system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
+system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
+system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
+system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::total 516803462 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed
-system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 5375859 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
+system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements 6005277 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits
-system.cpu0.dcache.overall_hits::total 140671079 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses
-system.cpu0.dcache.overall_misses::total 6183045 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks.
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.overall_hits::total 219752565 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 8782067 # number of ReadReq misses
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-system.cpu0.icache.overall_misses::total 8782067 # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::total 75181971221 # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_accesses::cpu0.inst 228534632 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::total 228534632 # number of overall (read+write) accesses
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-system.cpu0.icache.demand_miss_rate::total 0.038428 # miss rate for demand accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses
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+system.cpu0.icache.overall_hits::total 190986664 # number of overall hits
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+system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles
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+system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.ReadReq_mshr_misses::total 8782067 # number of ReadReq MSHR misses
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 61997855741 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61997855741 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 61997855741 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61997855741 # number of overall MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue
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-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page
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-system.cpu0.l2cache.tags.replacements 4037603 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id
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-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 146637664 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits
+system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 95196820 # DTB read hits
-system.cpu1.dtb.read_misses 258683 # DTB read misses
-system.cpu1.dtb.write_hits 82774540 # DTB write hits
-system.cpu1.dtb.write_misses 48918 # DTB write misses
+system.cpu1.dtb.read_hits 85144665 # DTB read hits
+system.cpu1.dtb.read_misses 232605 # DTB read misses
+system.cpu1.dtb.write_hits 73861979 # DTB write hits
+system.cpu1.dtb.write_misses 45370 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 95455503 # DTB read accesses
-system.cpu1.dtb.write_accesses 82823458 # DTB write accesses
+system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
+system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 177971360 # DTB hits
-system.cpu1.dtb.misses 307601 # DTB misses
-system.cpu1.dtb.accesses 178278961 # DTB accesses
+system.cpu1.dtb.hits 159006644 # DTB hits
+system.cpu1.dtb.misses 277975 # DTB misses
+system.cpu1.dtb.accesses 159284619 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 262373201 # ITB inst hits
-system.cpu1.itb.inst_misses 66107 # ITB inst misses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks 63204 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 184175570 # ITB inst hits
+system.cpu1.itb.inst_misses 63204 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses
-system.cpu1.itb.hits 262373201 # DTB hits
-system.cpu1.itb.misses 66107 # DTB misses
-system.cpu1.itb.accesses 262439308 # DTB accesses
-system.cpu1.numCycles 965776076 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
+system.cpu1.itb.hits 184175570 # DTB hits
+system.cpu1.itb.misses 63204 # DTB misses
+system.cpu1.itb.accesses 184238774 # DTB accesses
+system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 798693745 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 483897990 # Number of instructions committed
-system.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 1.995826 # CPI: cycles per instruction
-system.cpu1.ipc 0.501046 # IPC: instructions per cycle
+system.cpu1.committedInsts 398322797 # Number of instructions committed
+system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.005142 # CPI: cycles per instruction
+system.cpu1.ipc 0.498718 # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
+system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
+system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
+system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
+system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
+system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
+system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
+system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu1.op_class_0::total 474376671 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed
-system.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 5691678 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
+system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements 5132038 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits
-system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses
-system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 100449148266 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst 91914952 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 91914952 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst 79577330 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 79577330 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses)
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-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu1.dcache.writebacks::total 3739270 # number of writebacks
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 8498.421941 # average ReadReq miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency
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-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr
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-system.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit.
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor
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+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40348 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40348 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136740 # Transaction distribution
-system.iobus.trans_dist::WriteResp 30012 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
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-system.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles
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+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
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system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
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-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency
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-system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use
-system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks.
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-system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor
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-system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id
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-system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits
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-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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+system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 586564 # Total snoops (count)
+system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
+system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3975767 # Request fanout histogram
-system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2402773 # Request fanout histogram
+system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
+system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
+system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
+system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
+system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
+system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1718447 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
+system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
+system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
+system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3035429 # Total snoops (count)
+system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff