---------- Begin Simulation Statistics ----------
-sim_seconds 47.522770 # Number of seconds simulated
-sim_ticks 47522770414500 # Number of ticks simulated
-final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.405081 # Number of seconds simulated
+sim_ticks 47405080882500 # Number of ticks simulated
+final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 594104 # Simulator instruction rate (inst/s)
-host_op_rate 698838 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32027606991 # Simulator tick rate (ticks/s)
-host_mem_usage 752504 # Number of bytes of host memory used
-host_seconds 1483.81 # Real time elapsed on the host
-sim_insts 881535802 # Number of instructions simulated
-sim_ops 1036940641 # Number of ops (including micro ops) simulated
+host_inst_rate 1071981 # Simulator instruction rate (inst/s)
+host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57861452624 # Simulator tick rate (ticks/s)
+host_mem_usage 765552 # Number of bytes of host memory used
+host_seconds 819.29 # Real time elapsed on the host
+sim_insts 878258906 # Number of instructions simulated
+sim_ops 1033075205 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory
-system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory
+system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 925394 # Number of read requests accepted
-system.physmem.writeReqs 1177913 # Number of write requests accepted
-system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 927476 # Number of read requests accepted
+system.physmem.writeReqs 1170446 # Number of write requests accepted
+system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue
+system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 52385 # Per bank write bursts
-system.physmem.perBankRdBursts::1 62471 # Per bank write bursts
-system.physmem.perBankRdBursts::2 52469 # Per bank write bursts
-system.physmem.perBankRdBursts::3 57006 # Per bank write bursts
-system.physmem.perBankRdBursts::4 52192 # Per bank write bursts
-system.physmem.perBankRdBursts::5 61065 # Per bank write bursts
-system.physmem.perBankRdBursts::6 52770 # Per bank write bursts
-system.physmem.perBankRdBursts::7 53841 # Per bank write bursts
-system.physmem.perBankRdBursts::8 49119 # Per bank write bursts
-system.physmem.perBankRdBursts::9 95933 # Per bank write bursts
-system.physmem.perBankRdBursts::10 50791 # Per bank write bursts
-system.physmem.perBankRdBursts::11 57135 # Per bank write bursts
-system.physmem.perBankRdBursts::12 57588 # Per bank write bursts
-system.physmem.perBankRdBursts::13 62036 # Per bank write bursts
-system.physmem.perBankRdBursts::14 54549 # Per bank write bursts
-system.physmem.perBankRdBursts::15 53658 # Per bank write bursts
-system.physmem.perBankWrBursts::0 70290 # Per bank write bursts
-system.physmem.perBankWrBursts::1 77699 # Per bank write bursts
-system.physmem.perBankWrBursts::2 70837 # Per bank write bursts
-system.physmem.perBankWrBursts::3 75524 # Per bank write bursts
-system.physmem.perBankWrBursts::4 70767 # Per bank write bursts
-system.physmem.perBankWrBursts::5 75365 # Per bank write bursts
-system.physmem.perBankWrBursts::6 70544 # Per bank write bursts
-system.physmem.perBankWrBursts::7 72537 # Per bank write bursts
-system.physmem.perBankWrBursts::8 71114 # Per bank write bursts
-system.physmem.perBankWrBursts::9 74364 # Per bank write bursts
-system.physmem.perBankWrBursts::10 70757 # Per bank write bursts
-system.physmem.perBankWrBursts::11 75591 # Per bank write bursts
-system.physmem.perBankWrBursts::12 74466 # Per bank write bursts
-system.physmem.perBankWrBursts::13 78806 # Per bank write bursts
-system.physmem.perBankWrBursts::14 73579 # Per bank write bursts
-system.physmem.perBankWrBursts::15 73411 # Per bank write bursts
+system.physmem.perBankRdBursts::0 53525 # Per bank write bursts
+system.physmem.perBankRdBursts::1 58700 # Per bank write bursts
+system.physmem.perBankRdBursts::2 53136 # Per bank write bursts
+system.physmem.perBankRdBursts::3 59915 # Per bank write bursts
+system.physmem.perBankRdBursts::4 57558 # Per bank write bursts
+system.physmem.perBankRdBursts::5 67025 # Per bank write bursts
+system.physmem.perBankRdBursts::6 57593 # Per bank write bursts
+system.physmem.perBankRdBursts::7 57551 # Per bank write bursts
+system.physmem.perBankRdBursts::8 45941 # Per bank write bursts
+system.physmem.perBankRdBursts::9 94599 # Per bank write bursts
+system.physmem.perBankRdBursts::10 49635 # Per bank write bursts
+system.physmem.perBankRdBursts::11 57294 # Per bank write bursts
+system.physmem.perBankRdBursts::12 48522 # Per bank write bursts
+system.physmem.perBankRdBursts::13 56965 # Per bank write bursts
+system.physmem.perBankRdBursts::14 52794 # Per bank write bursts
+system.physmem.perBankRdBursts::15 56368 # Per bank write bursts
+system.physmem.perBankWrBursts::0 71875 # Per bank write bursts
+system.physmem.perBankWrBursts::1 75753 # Per bank write bursts
+system.physmem.perBankWrBursts::2 71549 # Per bank write bursts
+system.physmem.perBankWrBursts::3 77042 # Per bank write bursts
+system.physmem.perBankWrBursts::4 73392 # Per bank write bursts
+system.physmem.perBankWrBursts::5 80022 # Per bank write bursts
+system.physmem.perBankWrBursts::6 71461 # Per bank write bursts
+system.physmem.perBankWrBursts::7 73088 # Per bank write bursts
+system.physmem.perBankWrBursts::8 65465 # Per bank write bursts
+system.physmem.perBankWrBursts::9 74249 # Per bank write bursts
+system.physmem.perBankWrBursts::10 70475 # Per bank write bursts
+system.physmem.perBankWrBursts::11 74236 # Per bank write bursts
+system.physmem.perBankWrBursts::12 69250 # Per bank write bursts
+system.physmem.perBankWrBursts::13 75271 # Per bank write bursts
+system.physmem.perBankWrBursts::14 70641 # Per bank write bursts
+system.physmem.perBankWrBursts::15 74378 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 43 # Number of times write queue was full causing retry
-system.physmem.totGap 47522767065000 # Total gap between requests
+system.physmem.numWrRetry 399 # Number of times write queue was full causing retry
+system.physmem.totGap 47405077592000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 882169 # Read request sizes (log2)
+system.physmem.readPktSize::6 884251 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1175339 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1167872 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads
-system.physmem.totQLat 29196891613 # Total ticks spent queuing
-system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads
+system.physmem.totQLat 46391884854 # Total ticks spent queuing
+system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing
-system.physmem.readRowHits 690198 # Number of row buffer hits during reads
-system.physmem.writeRowHits 438618 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes
-system.physmem.avgGap 22594308.42 # Average gap between requests
-system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.652826 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.682174 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
+system.physmem.readRowHits 687053 # Number of row buffer hits during reads
+system.physmem.writeRowHits 479716 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes
+system.physmem.avgGap 22596205.96 # Average gap between requests
+system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ)
+system.physmem_0.averagePower 243.004907 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states
+system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ)
+system.physmem_1.averagePower 242.918480 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states
+system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 111522 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks 105104 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 86856517 # DTB read hits
-system.cpu0.dtb.read_misses 84644 # DTB read misses
-system.cpu0.dtb.write_hits 78666499 # DTB write hits
-system.cpu0.dtb.write_misses 26878 # DTB write misses
+system.cpu0.dtb.read_hits 85250979 # DTB read hits
+system.cpu0.dtb.read_misses 79026 # DTB read misses
+system.cpu0.dtb.write_hits 77401552 # DTB write hits
+system.cpu0.dtb.write_misses 26078 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 86941161 # DTB read accesses
-system.cpu0.dtb.write_accesses 78693377 # DTB write accesses
+system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 85330005 # DTB read accesses
+system.cpu0.dtb.write_accesses 77427630 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 165523016 # DTB hits
-system.cpu0.dtb.misses 111522 # DTB misses
-system.cpu0.dtb.accesses 165634538 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits 162652531 # DTB hits
+system.cpu0.dtb.misses 105104 # DTB misses
+system.cpu0.dtb.accesses 162757635 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 57441 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks 55600 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 461199865 # ITB inst hits
-system.cpu0.itb.inst_misses 57441 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 455710659 # ITB inst hits
+system.cpu0.itb.inst_misses 55600 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses
-system.cpu0.itb.hits 461199865 # DTB hits
-system.cpu0.itb.misses 57441 # DTB misses
-system.cpu0.itb.accesses 461257306 # DTB accesses
-system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 95045540829 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses
+system.cpu0.itb.hits 455710659 # DTB hits
+system.cpu0.itb.misses 55600 # DTB misses
+system.cpu0.itb.accesses 455766259 # DTB accesses
+system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 94809604801 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed
-system.cpu0.committedInsts 460929213 # Number of instructions committed
-system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses
-system.cpu0.num_func_calls 27781850 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 497492129 # number of integer instructions
-system.cpu0.num_fp_insts 434558 # number of float instructions
-system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written
-system.cpu0.num_mem_refs 165514046 # number of memory refs
-system.cpu0.num_load_insts 86852092 # Number of load instructions
-system.cpu0.num_store_insts 78661954 # Number of store instructions
-system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles
-system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles
-system.cpu0.Branches 102755128 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction
-system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction
-system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction
-system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction
+system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed
+system.cpu0.committedInsts 455440444 # Number of instructions committed
+system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses
+system.cpu0.num_func_calls 27345084 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 490602455 # number of integer instructions
+system.cpu0.num_fp_insts 409464 # number of float instructions
+system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written
+system.cpu0.num_mem_refs 162644052 # number of memory refs
+system.cpu0.num_load_insts 85246888 # Number of load instructions
+system.cpu0.num_store_insts 77397164 # Number of store instructions
+system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles
+system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles
+system.cpu0.Branches 101837898 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction
+system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction
+system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction
+system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction
+system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction
+system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 541493758 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 5689621 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits
-system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency
+system.cpu0.op_class::total 534571495 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements 5548235 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits
+system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses
+system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks
-system.cpu0.dcache.writebacks::total 5689621 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks
+system.cpu0.dcache.writebacks::total 5548235 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 5142905 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.icache.tags.replacements 4928137 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits
-system.cpu0.icache.overall_hits::total 456056448 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses
-system.cpu0.icache.overall_misses::total 5143417 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 461199865 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 461199865 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 461199865 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 461199865 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 461199865 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011152 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011152 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.011152 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011152 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.011152 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits
+system.cpu0.icache.overall_hits::total 450782010 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses
+system.cpu0.icache.overall_misses::total 4928649 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 5142905 # number of writebacks
-system.cpu0.icache.writebacks::total 5142905 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5143417 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 5143417 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 5143417 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 5143417 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 5143417 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 5143417 # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks
+system.cpu0.icache.writebacks::total 4928137 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51891596500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 51891596500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51891596500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 51891596500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51891596500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 51891596500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011152 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.011152 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.011152 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10088.934360 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
-system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency
+system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.tags.replacements 2348165 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.489283 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 784.884937 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.928250 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003776 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004852 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047906 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.984783 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14708 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 179 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 589 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 529 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses
-system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks 3764500 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total 3764500 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 7067152 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 7067152 # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 393 # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total 393 # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 904509 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 904509 # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4682717 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total 4682717 # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2902504 # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total 2902504 # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213097 # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total 213097 # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 263860 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148030 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 4682717 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 3807013 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 8901620 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 263860 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148030 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 4682717 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 3807013 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 8901620 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9421 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7390 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 16811 # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 243749 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 243749 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 205138 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 205138 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 251209 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 251209 # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 460700 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total 460700 # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 937841 # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total 937841 # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577609 # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total 577609 # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9421 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7390 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 460700 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 1189050 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 1666561 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9421 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7390 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 460700 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 1189050 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 1666561 # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 332469500 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 285177500 # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total 617647000 # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 1968962500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total 1968962500 # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1588151500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1588151500 # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2987000 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2987000 # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12588187000 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total 12588187000 # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 16045103500 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total 16045103500 # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 32885800500 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total 32885800500 # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 322469500 # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total 322469500 # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 332469500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 285177500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 16045103500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data 45473987500 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total 62136738000 # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 332469500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 285177500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst 16045103500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data 45473987500 # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total 62136738000 # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 273281 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155420 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 428701 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3764500 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total 3764500 # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks 7067152 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total 7067152 # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244142 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 244142 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 205138 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 205138 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1155718 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 1155718 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5143417 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total 5143417 # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3840345 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total 3840345 # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790706 # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total 790706 # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 273281 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155420 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 5143417 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 4996063 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 10568181 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 273281 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155420 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 5143417 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 4996063 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 10568181 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047549 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.039214 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998390 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998390 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.tags.replacements 2238289 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses
+system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits
+system.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses
+system.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217362 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217362 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089571 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089571 # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244207 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244207 # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730498 # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730498 # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047549 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089571 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237997 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.157696 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047549 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089571 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237997 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.157696 # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38589.648173 # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36740.646006 # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8077.828012 # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8077.828012 # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7741.868888 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7741.868888 # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 373375 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 373375 # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50110.414038 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50110.414038 # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34827.661168 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34827.661168 # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35065.432733 # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35065.432733 # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 558.283372 # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 558.283372 # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 37284.406631 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 37284.406631 # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.unused_prefetches 37568 # number of HardPF blocks evicted w/o reference
-system.cpu0.l2cache.writebacks::writebacks 1506522 # number of writebacks
-system.cpu0.l2cache.writebacks::total 1506522 # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5548 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total 5548 # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 408 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 408 # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5956 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total 5956 # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5956 # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total 5956 # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9421 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7390 # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total 16811 # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total 719381 # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 243749 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total 243749 # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 205138 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 205138 # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 245661 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total 245661 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 460700 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 460700 # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 937433 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 937433 # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577609 # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577609 # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9421 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7390 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 460700 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1183094 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 1660605 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9421 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7390 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 460700 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1183094 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 2379986 # number of overall MSHR misses
+system.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference
+system.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks
+system.cpu0.l2cache.writebacks::total 1501692 # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70742 # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97307 # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 240837500 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 516781000 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32427966574 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5063458500 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5063458500 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3348331499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3348331499 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2645000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2645000 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10596762500 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10596762500 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13280903500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13280903500 # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27229516500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27229516500 # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18926305000 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18926305000 # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 240837500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13280903500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37826279000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 51623963500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 240837500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13280903500 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37826279000 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 84051930074 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850886500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346919000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998390 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998390 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730498 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency
-system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 105013 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks 105151 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 79229823 # DTB read hits
-system.cpu1.dtb.read_misses 76992 # DTB read misses
-system.cpu1.dtb.write_hits 72255246 # DTB write hits
-system.cpu1.dtb.write_misses 28021 # DTB write misses
+system.cpu1.dtb.read_hits 80227147 # DTB read hits
+system.cpu1.dtb.read_misses 76874 # DTB read misses
+system.cpu1.dtb.write_hits 72873093 # DTB write hits
+system.cpu1.dtb.write_misses 28277 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 79306815 # DTB read accesses
-system.cpu1.dtb.write_accesses 72283267 # DTB write accesses
+system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 80304021 # DTB read accesses
+system.cpu1.dtb.write_accesses 72901370 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 151485069 # DTB hits
-system.cpu1.dtb.misses 105013 # DTB misses
-system.cpu1.dtb.accesses 151590082 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits 153100240 # DTB hits
+system.cpu1.dtb.misses 105151 # DTB misses
+system.cpu1.dtb.accesses 153205391 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 58945 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks 60537 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 420888418 # ITB inst hits
-system.cpu1.itb.inst_misses 58945 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 423099313 # ITB inst hits
+system.cpu1.itb.inst_misses 60537 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses
-system.cpu1.itb.hits 420888418 # DTB hits
-system.cpu1.itb.misses 58945 # DTB misses
-system.cpu1.itb.accesses 420947363 # DTB accesses
-system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 95045540824 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses
+system.cpu1.itb.hits 423099313 # DTB hits
+system.cpu1.itb.misses 60537 # DTB misses
+system.cpu1.itb.accesses 423159850 # DTB accesses
+system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 94810161765 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed
-system.cpu1.committedInsts 420606589 # Number of instructions committed
-system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses
-system.cpu1.num_func_calls 25050170 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 455422102 # number of integer instructions
-system.cpu1.num_fp_insts 465343 # number of float instructions
-system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written
-system.cpu1.num_mem_refs 151477231 # number of memory refs
-system.cpu1.num_load_insts 79227868 # Number of load instructions
-system.cpu1.num_store_insts 72249363 # Number of store instructions
-system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles
-system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles
-system.cpu1.Branches 93889993 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction
-system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction
-system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction
-system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction
-system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction
+system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed
+system.cpu1.committedInsts 422818462 # Number of instructions committed
+system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses
+system.cpu1.num_func_calls 25225246 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 458669371 # number of integer instructions
+system.cpu1.num_fp_insts 488965 # number of float instructions
+system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written
+system.cpu1.num_mem_refs 153090665 # number of memory refs
+system.cpu1.num_load_insts 80223644 # Number of load instructions
+system.cpu1.num_store_insts 72867021 # Number of store instructions
+system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles
+system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles
+system.cpu1.Branches 94103649 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction
+system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction
+system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction
+system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction
+system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 496042597 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 5018466 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits
-system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency
+system.cpu1.op_class::total 499098010 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements 5131141 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits
+system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses
+system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks
-system.cpu1.dcache.writebacks::total 5018466 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 16365 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 405 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 405 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42163 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42163 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 16770 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 16770 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 16770 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 16770 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2821665 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 2821665 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1310222 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks
+system.cpu1.dcache.writebacks::total 5131141 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 4797887 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency
+system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.icache.tags.replacements 5003710 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits
-system.cpu1.icache.overall_hits::total 416090013 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses
-system.cpu1.icache.overall_misses::total 4798405 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 420888418 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 420888418 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 420888418 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011401 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.011401 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011401 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.011401 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011401 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.011401 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10628.213542 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10628.213542 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10628.213542 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses
+system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits
+system.cpu1.icache.overall_hits::total 418095086 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses
+system.cpu1.icache.overall_misses::total 5004227 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 4797887 # number of writebacks
-system.cpu1.icache.writebacks::total 4797887 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4798405 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 4798405 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 4798405 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 4798405 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 4798405 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 4798405 # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks
+system.cpu1.icache.writebacks::total 5003710 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48599271000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 48599271000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48599271000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 48599271000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48599271000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 48599271000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011401 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.011401 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.011401 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency
-system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency
+system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.tags.replacements 1970256 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 64.411311 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 905.409563 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.749966 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002697 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003931 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055262 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.811856 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1582 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13889 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 38 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses
-system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total 549 # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 848093 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 848093 # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4339488 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total 4339488 # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2669176 # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total 2669176 # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193952 # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total 193952 # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 241732 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150683 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 4339488 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 3517269 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 8249172 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 241732 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150683 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 4339488 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 3517269 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 8249172 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10752 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9335 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 20087 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 209731 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 209731 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 204666 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 204666 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253892 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 253892 # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458917 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total 458917 # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 897743 # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total 897743 # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252003 # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total 252003 # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10752 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9335 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 458917 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 1151635 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 1630639 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10752 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9335 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 458917 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 1151635 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 1630639 # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 421263500 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 385353500 # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total 806617000 # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1909199500 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total 1909199500 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1509536500 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1509536500 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2962499 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2962499 # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10235182000 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total 10235182000 # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15333921500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15333921500 # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29041295500 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29041295500 # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 413814500 # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total 413814500 # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 421263500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 385353500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15333921500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data 39276477500 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total 55417016000 # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 421263500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 385353500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15333921500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data 39276477500 # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total 55417016000 # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 252484 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160018 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 412502 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3174179 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total 3174179 # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks 6641283 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total 6641283 # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 210280 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 210280 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204666 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 204666 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 10 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1101985 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 1101985 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4798405 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total 4798405 # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3566919 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total 3566919 # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 445955 # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total 445955 # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 252484 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160018 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 4798405 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 4668904 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 9879811 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 252484 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160018 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 4798405 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 4668904 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 9879811 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.048696 # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997389 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997389 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.tags.replacements 1888854 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses
+system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits
+system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses
+system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230395 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230395 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095639 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095639 # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.251686 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.251686 # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565086 # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565086 # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095639 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246661 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.165048 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095639 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246661 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.165048 # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41280.503482 # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 40156.170658 # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9103.086811 # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9103.086811 # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7375.609530 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7375.609530 # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 296249.900000 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 296249.900000 # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40313.133143 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40313.133143 # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33413.278436 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33413.278436 # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32349.230793 # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32349.230793 # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1642.101483 # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1642.101483 # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 33984.846431 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 33984.846431 # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.unused_prefetches 39843 # number of HardPF blocks evicted w/o reference
-system.cpu1.l2cache.writebacks::writebacks 1100180 # number of writebacks
-system.cpu1.l2cache.writebacks::total 1100180 # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4729 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total 4729 # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 266 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 266 # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4995 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total 4995 # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4995 # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total 4995 # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10752 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9335 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 20087 # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total 687556 # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 209731 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 209731 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 204666 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 204666 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 10 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249163 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total 249163 # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 458917 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 458917 # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 897477 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 897477 # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252001 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252001 # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10752 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9335 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 458917 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1146640 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total 1625644 # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10752 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9335 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 458917 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1146640 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total 2313200 # number of overall MSHR misses
+system.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference
+system.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks
+system.cpu1.l2cache.writebacks::total 1086447 # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11145 # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23094 # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329343500 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 686095000 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27876431726 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4396610500 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4396610500 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3329007000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3329007000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2614499 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2614499 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8260901500 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8260901500 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12580419500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12580419500 # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23624853500 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23624853500 # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6839135500 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6839135500 # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329343500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12580419500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31885755000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 45152269500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329343500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12580419500 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31885755000 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 73028701226 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1805437500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1814839000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1805437500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1814839000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048696 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997389 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997389 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226104 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226104 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095639 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251611 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251611 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565082 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565082 # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164542 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency
-system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 40383 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40383 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115585 # number of replacements
-system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements 115614 # number of replacements
+system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040784 # Number of tag accesses
-system.iocache.tags.data_accesses 1040784 # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.iocache.tags.tag_accesses 1041054 # Number of tag accesses
+system.iocache.tags.data_accesses 1041054 # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses
-system.iocache.demand_misses::total 115643 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses
+system.iocache.demand_misses::total 115673 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 115603 # number of overall misses
-system.iocache.overall_misses::total 115643 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide 115633 # number of overall misses
+system.iocache.overall_misses::total 115673 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks 106695 # number of writebacks
-system.iocache.writebacks::total 106695 # number of writebacks
+system.iocache.writebacks::writebacks 106694 # number of writebacks
+system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 115603 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 115643 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 115603 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 115643 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179481612 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1182831112 # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7559977711 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 7559977711 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 8739459323 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8743027823 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 1336257 # number of replacements
-system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use
-system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 220.083460 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4065.866850 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 8220.853874 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.282047 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.986041 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.004111 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.044752 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.078070 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.163171 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.964958 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 10513 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 47867 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 208 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 519 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 9786 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 69855982 # Number of tag accesses
-system.l2c.tags.data_accesses 69855982 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 45889 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 57251 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 103140 # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4670 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3337 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst 411404 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 536957 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 268808 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6004 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5313 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst 419752 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 541221 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283166 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 2480632 # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data 118921 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data 122409 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total 241330 # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 4670 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3337 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 411404 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 582846 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 268808 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 6004 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 5313 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 419752 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 598472 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 283166 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2583772 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 4670 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 3337 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 411404 # number of overall hits
-system.l2c.overall_hits::cpu0.data 582846 # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher 268808 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 6004 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 5313 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 419752 # number of overall hits
-system.l2c.overall_hits::cpu1.data 598472 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 283166 # number of overall hits
-system.l2c.overall_hits::total 2583772 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 61222 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 59774 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 120996 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 13056 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 12621 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 25677 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 80578 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 52729 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133307 # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1507 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst 49296 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 137179 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2116 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst 39165 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 95585 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 747356 # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data 446352 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data 114497 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total 560849 # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 1465 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 1507 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 49296 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 217757 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 2146 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 2116 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 39165 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 148314 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) misses
-system.l2c.demand_misses::total 880663 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 1465 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 1507 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 49296 # number of overall misses
-system.l2c.overall_misses::cpu0.data 217757 # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher 229932 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 2146 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 2116 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 39165 # number of overall misses
-system.l2c.overall_misses::cpu1.data 148314 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 188965 # number of overall misses
-system.l2c.overall_misses::total 880663 # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data 367859500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 359764000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 727623500 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 70353500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 71619000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 141972500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 7055893500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4403905000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 11459798500 # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131430500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 136636000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst 4206937000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data 12205051500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 192694000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 194855000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3362110000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 8709641000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 79366262993 # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data 47144000 # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data 45361000 # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total 92505000 # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 131430500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker 136636000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 4206937000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 19260945000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 192694000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 194855000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 3362110000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 13113546000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 90826061493 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 131430500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker 136636000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 4206937000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 19260945000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 192694000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 194855000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 3362110000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 13113546000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 90826061493 # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks 2606701 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 2606701 # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 219171 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 190208 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 409379 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 49884 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 49655 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 99539 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 126467 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 109980 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 236447 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6135 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4844 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst 460700 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 674136 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 498740 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8150 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7429 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst 458917 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 636806 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 472131 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 3227988 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data 565273 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data 236906 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total 802179 # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 6135 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 4844 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 460700 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 800603 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher 498740 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 8150 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 458917 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 746786 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher 472131 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3464435 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 6135 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 4844 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 460700 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 800603 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher 498740 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 8150 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 458917 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 746786 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher 472131 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3464435 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.279334 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.314256 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.295560 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.261727 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.254174 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.257959 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.637146 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.479442 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.563792 # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311107 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107002 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203489 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.284830 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085342 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.150101 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.231524 # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789622 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data 0.483301 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total 0.699157 # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.311107 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.107002 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.271991 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.284830 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.085342 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.198603 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.254201 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.311107 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.107002 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.271991 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.284830 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.085342 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.198603 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.254201 # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6008.616184 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6018.737244 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 6013.616153 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5388.595282 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5674.589969 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 5529.170074 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87566.004368 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83519.600220 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 85965.466930 # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90667.551427 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85340.331873 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88971.719432 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92086.483932 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85844.759351 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91119.328346 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 106196.060503 # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 105.620676 # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 396.176319 # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 164.937443 # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 103133.731624 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 103133.731624 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 237 # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.l2c.tags.replacements 1381741 # number of replacements
+system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use
+system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 67794643 # Number of tag accesses
+system.l2c.tags.data_accesses 67794643 # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2537328 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 389694 # number of overall hits
+system.l2c.overall_hits::cpu0.data 556846 # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 424247 # number of overall hits
+system.l2c.overall_hits::cpu1.data 597655 # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits
+system.l2c.overall_hits::total 2537328 # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses
+system.l2c.demand_misses::total 879096 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 53195 # number of overall misses
+system.l2c.overall_misses::cpu0.data 218373 # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 39604 # number of overall misses
+system.l2c.overall_misses::cpu1.data 151830 # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses
+system.l2c.overall_misses::total 879096 # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs 237 # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks 1068644 # number of writebacks
-system.l2c.writebacks::total 1068644 # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 42 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data 7 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 109 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data 24 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 182 # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 7 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 109 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 7 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 182 # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks 46836 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 46836 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 61222 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 59774 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 120996 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13056 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12621 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 25677 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 80578 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 52729 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 133307 # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1507 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 49254 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data 137172 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2116 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39056 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 95561 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 747174 # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data 446352 # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data 114497 # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total 560849 # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 1465 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker 1507 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 49254 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 217750 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 2146 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 2116 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 39056 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 148290 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 880481 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 1465 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker 1507 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 49254 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 217750 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 2146 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 2116 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 39056 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 148290 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 880481 # number of overall MSHR misses
+system.l2c.writebacks::writebacks 1061178 # number of writebacks
+system.l2c.writebacks::total 1061178 # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11033 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 81885 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 38514 # number of WriteReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22982 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 120399 # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1334926500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1302438000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 2637364500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 323030000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 313272000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 636302000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6250073584 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3876565100 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 10126638684 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 121565002 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3711112036 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10832879176 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 173694002 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 2962814058 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7752148763 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 71879702509 # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8910827500 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2333318000 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total 11244145500 # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 121565002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 3711112036 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 17082952760 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173694002 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 2962814058 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 11628713863 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 82006341193 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 121565002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 3711112036 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 17082952760 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173694002 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 2962814058 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 11628713863 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 82006341193 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4353667507 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7421000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1606781004 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 8687651511 # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4353667507 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7421000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1606781004 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 8687651511 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 12432086139 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 140574501 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5355219542 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14279847185 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 196268502 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4312153532 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 21714443231 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 196268502 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 4312153532 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 15765200265 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 98637178589 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4911881502 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 8111000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1045413500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 8982252002 # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.279334 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.314256 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.295560 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.261727 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.254174 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257959 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.637146 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.479442 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.563792 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.203478 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.150063 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231467 # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789622 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.483301 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.699157 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.254149 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.254149 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 81885 # Transaction distribution
-system.membus.trans_dist::ReadResp 837971 # Transaction distribution
-system.membus.trans_dist::WriteReq 38514 # Transaction distribution
-system.membus.trans_dist::WriteResp 38514 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution
-system.membus.trans_dist::CleanEvict 216465 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq 81785 # Transaction distribution
+system.membus.trans_dist::ReadResp 843578 # Transaction distribution
+system.membus.trans_dist::WriteReq 38414 # Transaction distribution
+system.membus.trans_dist::WriteResp 38414 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution
+system.membus.trans_dist::CleanEvict 225685 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 147056 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129063 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 142258 # Transaction distribution
+system.membus.trans_dist::ReadExResp 125306 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution
+system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 605187 # Total snoops (count)
-system.membus.snoop_fanout::samples 2426230 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 601899 # Total snoops (count)
+system.membus.snoopTraffic 182272 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2241138 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram
-system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram
+system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2426230 # Request fanout histogram
-system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2241138 # Request fanout histogram
+system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2781791 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2851175 # Total snoops (count)
+system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff