---------- Begin Simulation Statistics ----------
-sim_seconds 47.579919 # Number of seconds simulated
-sim_ticks 47579919171500 # Number of ticks simulated
-final_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.405081 # Number of seconds simulated
+sim_ticks 47405080882500 # Number of ticks simulated
+final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 994477 # Simulator instruction rate (inst/s)
-host_op_rate 1169790 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52043300787 # Simulator tick rate (ticks/s)
-host_mem_usage 760992 # Number of bytes of host memory used
-host_seconds 914.24 # Real time elapsed on the host
-sim_insts 909188095 # Number of instructions simulated
-sim_ops 1069465904 # Number of ops (including micro ops) simulated
+host_inst_rate 1071981 # Simulator instruction rate (inst/s)
+host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57861452624 # Simulator tick rate (ticks/s)
+host_mem_usage 765552 # Number of bytes of host memory used
+host_seconds 819.29 # Real time elapsed on the host
+sim_insts 878258906 # Number of instructions simulated
+sim_ops 1033075205 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 66121412 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory
+system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 84323880 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1073668 # Number of read requests accepted
-system.physmem.writeReqs 1319813 # Number of write requests accepted
-system.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue
-system.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 927476 # Number of read requests accepted
+system.physmem.writeReqs 1170446 # Number of write requests accepted
+system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue
+system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 64017 # Per bank write bursts
-system.physmem.perBankRdBursts::1 68044 # Per bank write bursts
-system.physmem.perBankRdBursts::2 61517 # Per bank write bursts
-system.physmem.perBankRdBursts::3 65955 # Per bank write bursts
-system.physmem.perBankRdBursts::4 65874 # Per bank write bursts
-system.physmem.perBankRdBursts::5 75726 # Per bank write bursts
-system.physmem.perBankRdBursts::6 64933 # Per bank write bursts
-system.physmem.perBankRdBursts::7 65424 # Per bank write bursts
-system.physmem.perBankRdBursts::8 62003 # Per bank write bursts
-system.physmem.perBankRdBursts::9 113372 # Per bank write bursts
-system.physmem.perBankRdBursts::10 63434 # Per bank write bursts
-system.physmem.perBankRdBursts::11 64718 # Per bank write bursts
-system.physmem.perBankRdBursts::12 56904 # Per bank write bursts
-system.physmem.perBankRdBursts::13 64084 # Per bank write bursts
-system.physmem.perBankRdBursts::14 56898 # Per bank write bursts
-system.physmem.perBankRdBursts::15 60394 # Per bank write bursts
-system.physmem.perBankWrBursts::0 80527 # Per bank write bursts
-system.physmem.perBankWrBursts::1 85904 # Per bank write bursts
-system.physmem.perBankWrBursts::2 80420 # Per bank write bursts
-system.physmem.perBankWrBursts::3 86054 # Per bank write bursts
-system.physmem.perBankWrBursts::4 85401 # Per bank write bursts
-system.physmem.perBankWrBursts::5 88715 # Per bank write bursts
-system.physmem.perBankWrBursts::6 80808 # Per bank write bursts
-system.physmem.perBankWrBursts::7 81222 # Per bank write bursts
-system.physmem.perBankWrBursts::8 80522 # Per bank write bursts
-system.physmem.perBankWrBursts::9 87926 # Per bank write bursts
-system.physmem.perBankWrBursts::10 79616 # Per bank write bursts
-system.physmem.perBankWrBursts::11 81105 # Per bank write bursts
-system.physmem.perBankWrBursts::12 77689 # Per bank write bursts
-system.physmem.perBankWrBursts::13 84231 # Per bank write bursts
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-system.physmem.perBankWrBursts::15 80134 # Per bank write bursts
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+system.physmem.perBankWrBursts::9 74249 # Per bank write bursts
+system.physmem.perBankWrBursts::10 70475 # Per bank write bursts
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+system.physmem.perBankWrBursts::12 69250 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 70641 # Per bank write bursts
+system.physmem.perBankWrBursts::15 74378 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 116 # Number of times write queue was full causing retry
-system.physmem.totGap 47579915806000 # Total gap between requests
+system.physmem.numWrRetry 399 # Number of times write queue was full causing retry
+system.physmem.totGap 47405077592000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1030443 # Read request sizes (log2)
+system.physmem.readPktSize::6 884251 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1317239 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 761963 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 94096 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 44762 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 138 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1167872 # Write request sizes (log2)
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 138.133954 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 23731 2.14% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1107709 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 15.125666 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 121.252784 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 70954 99.99% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 18.567688 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.991036 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.306981 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 58539 82.50% 82.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 9965 14.04% 96.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 642 0.90% 97.45% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::36-39 121 0.17% 98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 191 0.27% 98.33% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::60-63 42 0.06% 99.04% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::76-79 116 0.16% 99.67% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads
-system.physmem.totQLat 35332291342 # Total ticks spent queuing
-system.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads
+system.physmem.totQLat 46391884854 # Total ticks spent queuing
+system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
-system.physmem.readRowHits 793862 # Number of row buffer hits during reads
-system.physmem.writeRowHits 489250 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes
-system.physmem.avgGap 19878961.15 # Average gap between requests
-system.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.795690 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.771738 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
+system.physmem.readRowHits 687053 # Number of row buffer hits during reads
+system.physmem.writeRowHits 479716 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes
+system.physmem.avgGap 22596205.96 # Average gap between requests
+system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ)
+system.physmem_0.averagePower 243.004907 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states
+system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ)
+system.physmem_1.averagePower 242.918480 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states
+system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 116306 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks 105104 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 86290817 # DTB read hits
-system.cpu0.dtb.read_misses 86990 # DTB read misses
-system.cpu0.dtb.write_hits 77965379 # DTB write hits
-system.cpu0.dtb.write_misses 29316 # DTB write misses
+system.cpu0.dtb.read_hits 85250979 # DTB read hits
+system.cpu0.dtb.read_misses 79026 # DTB read misses
+system.cpu0.dtb.write_hits 77401552 # DTB write hits
+system.cpu0.dtb.write_misses 26078 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 86377807 # DTB read accesses
-system.cpu0.dtb.write_accesses 77994695 # DTB write accesses
+system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 85330005 # DTB read accesses
+system.cpu0.dtb.write_accesses 77427630 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 164256196 # DTB hits
-system.cpu0.dtb.misses 116306 # DTB misses
-system.cpu0.dtb.accesses 164372502 # DTB accesses
+system.cpu0.dtb.hits 162652531 # DTB hits
+system.cpu0.dtb.misses 105104 # DTB misses
+system.cpu0.dtb.accesses 162757635 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 53337 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks 55600 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 461259285 # ITB inst hits
-system.cpu0.itb.inst_misses 53337 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 455710659 # ITB inst hits
+system.cpu0.itb.inst_misses 55600 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 461312622 # ITB inst accesses
-system.cpu0.itb.hits 461259285 # DTB hits
-system.cpu0.itb.misses 53337 # DTB misses
-system.cpu0.itb.accesses 461312622 # DTB accesses
-system.cpu0.numCycles 95159838338 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses
+system.cpu0.itb.hits 455710659 # DTB hits
+system.cpu0.itb.misses 55600 # DTB misses
+system.cpu0.itb.accesses 455766259 # DTB accesses
+system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 94809604801 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed
-system.cpu0.committedInsts 460977499 # Number of instructions committed
-system.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses
-system.cpu0.num_func_calls 27096084 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 495872658 # number of integer instructions
-system.cpu0.num_fp_insts 377758 # number of float instructions
-system.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written
-system.cpu0.num_mem_refs 164249297 # number of memory refs
-system.cpu0.num_load_insts 86287437 # Number of load instructions
-system.cpu0.num_store_insts 77961860 # Number of store instructions
-system.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles
-system.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.987161 # Percentage of idle cycles
-system.cpu0.Branches 102925889 # Number of branches fetched
+system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed
+system.cpu0.committedInsts 455440444 # Number of instructions committed
+system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses
+system.cpu0.num_func_calls 27345084 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 490602455 # number of integer instructions
+system.cpu0.num_fp_insts 409464 # number of float instructions
+system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written
+system.cpu0.num_mem_refs 162644052 # number of memory refs
+system.cpu0.num_load_insts 85246888 # Number of load instructions
+system.cpu0.num_store_insts 77397164 # Number of store instructions
+system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles
+system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles
+system.cpu0.Branches 101837898 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction
-system.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction
-system.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction
+system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction
+system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction
+system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction
+system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction
+system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 541013060 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 5729731 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits
-system.cpu0.dcache.overall_hits::total 153932821 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5223943 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49559521500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 49559521500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2516267500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2516267500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5589291500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 5589291500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2738500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2738500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 90800968500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 90800968500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 90800968500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 90800968500 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 83324174 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 83324174 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 74936215 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 74936215 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 896375 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 896375 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 953537 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 953537 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2041774 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2041774 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2040330 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2040330 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 158260389 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 158260389 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 159156764 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 159156764 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036964 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036964 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019323 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.019323 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.776409 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.776409 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.806155 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.806155 # miss rate for WriteLineReq accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077614 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097109 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097109 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.028611 # miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568 # average StoreCondReq miss latency
+system.cpu0.op_class::total 534571495 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements 5548235 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
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+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20053.266141 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17381.692048 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 5729731 # number of writebacks
-system.cpu0.dcache.writebacks::total 5729731 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28073 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 28073 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21239 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 21239 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41058 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117412 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117412 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 198134 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 56385 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47315434500 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 83700430500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5280351500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036627 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency
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-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 4741257 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks.
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
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-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.778461 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168169 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6577979 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency
+system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count)
+system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes)
+system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 108188 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks 105151 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 84911532 # DTB read hits
-system.cpu1.dtb.read_misses 79075 # DTB read misses
-system.cpu1.dtb.write_hits 77663318 # DTB write hits
-system.cpu1.dtb.write_misses 29113 # DTB write misses
+system.cpu1.dtb.read_hits 80227147 # DTB read hits
+system.cpu1.dtb.read_misses 76874 # DTB read misses
+system.cpu1.dtb.write_hits 72873093 # DTB write hits
+system.cpu1.dtb.write_misses 28277 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 84990607 # DTB read accesses
-system.cpu1.dtb.write_accesses 77692431 # DTB write accesses
+system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 80304021 # DTB read accesses
+system.cpu1.dtb.write_accesses 72901370 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 162574850 # DTB hits
-system.cpu1.dtb.misses 108188 # DTB misses
-system.cpu1.dtb.accesses 162683038 # DTB accesses
+system.cpu1.dtb.hits 153100240 # DTB hits
+system.cpu1.dtb.misses 105151 # DTB misses
+system.cpu1.dtb.accesses 153205391 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 63937 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks 60537 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 448499634 # ITB inst hits
-system.cpu1.itb.inst_misses 63937 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 423099313 # ITB inst hits
+system.cpu1.itb.inst_misses 60537 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 448563571 # ITB inst accesses
-system.cpu1.itb.hits 448499634 # DTB hits
-system.cpu1.itb.misses 63937 # DTB misses
-system.cpu1.itb.accesses 448563571 # DTB accesses
-system.cpu1.numCycles 95159838343 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses
+system.cpu1.itb.hits 423099313 # DTB hits
+system.cpu1.itb.misses 60537 # DTB misses
+system.cpu1.itb.accesses 423159850 # DTB accesses
+system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 94810161765 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed
-system.cpu1.committedInsts 448210596 # Number of instructions committed
-system.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses
-system.cpu1.num_func_calls 27136019 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 486415785 # number of integer instructions
-system.cpu1.num_fp_insts 519922 # number of float instructions
-system.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written
-system.cpu1.num_mem_refs 162566757 # number of memory refs
-system.cpu1.num_load_insts 84909557 # Number of load instructions
-system.cpu1.num_store_insts 77657200 # Number of store instructions
-system.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles
-system.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988289 # Percentage of idle cycles
-system.cpu1.Branches 99989008 # Number of branches fetched
+system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed
+system.cpu1.committedInsts 422818462 # Number of instructions committed
+system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses
+system.cpu1.num_func_calls 25225246 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 458669371 # number of integer instructions
+system.cpu1.num_fp_insts 488965 # number of float instructions
+system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written
+system.cpu1.num_mem_refs 153090665 # number of memory refs
+system.cpu1.num_load_insts 80223644 # Number of load instructions
+system.cpu1.num_store_insts 72867021 # Number of store instructions
+system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles
+system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles
+system.cpu1.Branches 94103649 # Number of branches fetched
system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction
-system.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction
-system.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction
+system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction
+system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction
+system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction
+system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction
+system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction
+system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 529066901 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 5332630 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy
+system.cpu1.op_class::total 499098010 # Class of executed instruction
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.replacements 5131141 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits
-system.cpu1.dcache.overall_hits::total 152980241 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5054936 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066969 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15490.898439 # average ReadReq mshr miss latency
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598 # average WriteReq mshr miss latency
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-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34924.961541 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14710.581247 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649 # average StoreCondReq mshr miss latency
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323 # average overall mshr miss latency
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-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297 # average ReadReq mshr uncacheable latency
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-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432 # average overall mshr uncacheable latency
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 10933.327473 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency::total 10933.327473 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency
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-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency
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-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5987251 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency
+system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count)
+system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes)
+system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40370 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40370 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136628 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136628 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
+system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 40383 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40383 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.805617 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.484635 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.711379 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.279701 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.279701 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70645.608157 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70822.845472 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70734.817393 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73734.473584 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73731.803576 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73733.082159 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127628.243439 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124096.831143 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 126163.836968 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129476.889559 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131038.589718 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146856.147423 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68924.750887 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919 # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 81896 # Transaction distribution
-system.membus.trans_dist::ReadResp 974121 # Transaction distribution
-system.membus.trans_dist::WriteReq 38489 # Transaction distribution
-system.membus.trans_dist::WriteResp 38489 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution
-system.membus.trans_dist::CleanEvict 246913 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 405326 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses
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+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency
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+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadReq 81785 # Transaction distribution
+system.membus.trans_dist::ReadResp 843578 # Transaction distribution
+system.membus.trans_dist::WriteReq 38414 # Transaction distribution
+system.membus.trans_dist::WriteResp 38414 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution
+system.membus.trans_dist::CleanEvict 225685 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 159351 # Transaction distribution
-system.membus.trans_dist::ReadExResp 141190 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 691970 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
+system.membus.trans_dist::ReadExReq 142258 # Transaction distribution
+system.membus.trans_dist::ReadExResp 125306 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution
+system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 585601 # Total snoops (count)
-system.membus.snoop_fanout::samples 4153558 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 601899 # Total snoops (count)
+system.membus.snoopTraffic 182272 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 2241138 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram
+system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4153558 # Request fanout histogram
-system.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2241138 # Request fanout histogram
+system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3137723 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2851175 # Total snoops (count)
+system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff