---------- Begin Simulation Statistics ----------
-sim_seconds 5.132970 # Number of seconds simulated
-sim_ticks 5132969930500 # Number of ticks simulated
-final_tick 5132969930500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.230834 # Number of seconds simulated
+sim_ticks 5230834315000 # Number of ticks simulated
+final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124251 # Simulator instruction rate (inst/s)
-host_op_rate 245606 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1563205434 # Simulator tick rate (ticks/s)
-host_mem_usage 769808 # Number of bytes of host memory used
-host_seconds 3283.62 # Real time elapsed on the host
-sim_insts 407992820 # Number of instructions simulated
-sim_ops 806477449 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2455424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1078336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10828544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14365568 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1078336 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1078336 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9561728 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9561728 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38366 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16849 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169196 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224462 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149402 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149402 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 478363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 561 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 210080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2109606 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2798685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 210080 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 210080 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1862806 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1862806 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1862806 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 478363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 561 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 210080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2109606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4661492 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 224462 # Total number of read requests seen
-system.physmem.writeReqs 149402 # Total number of write requests seen
-system.physmem.cpureqs 377855 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14365568 # Total number of bytes read from memory
-system.physmem.bytesWritten 9561728 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14365568 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9561728 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 117 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3983 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14085 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13102 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 13279 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 16301 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13529 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13167 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13352 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 13149 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13590 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 15875 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13170 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12525 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 13306 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15771 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9020 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 8543 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8624 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 11619 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8620 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 11646 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 9037 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8560 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 8885 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 11311 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8333 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8041 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8600 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 11074 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5132969877000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 224462 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 149402 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 173725 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 19496 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3528 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3016 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1787 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1703 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1643 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1099 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 996 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 849 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 783 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 765 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 852 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 836 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 389 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 218 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+host_inst_rate 207627 # Simulator instruction rate (inst/s)
+host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
+host_mem_usage 751184 # Number of bytes of host memory used
+host_seconds 1964.86 # Real time elapsed on the host
+sim_insts 407959263 # Number of instructions simulated
+sim_ops 806441023 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory
+system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 181488 # Number of read requests accepted
+system.physmem.writeReqs 145215 # Number of write requests accepted
+system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11156 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11363 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11879 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11399 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11231 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10765 # Per bank write bursts
+system.physmem.perBankRdBursts::6 10426 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10967 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10953 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10767 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11374 # Per bank write bursts
+system.physmem.perBankRdBursts::11 11178 # Per bank write bursts
+system.physmem.perBankRdBursts::12 12058 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12613 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11821 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11247 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9305 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9167 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9550 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8690 # Per bank write bursts
+system.physmem.perBankWrBursts::4 9047 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8333 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8814 # Per bank write bursts
+system.physmem.perBankWrBursts::8 9019 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9026 # Per bank write bursts
+system.physmem.perBankWrBursts::10 9076 # Per bank write bursts
+system.physmem.perBankWrBursts::11 9210 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9034 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9456 # Per bank write bursts
+system.physmem.perBankWrBursts::15 9034 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 5230834265500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 181488 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 145215 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 5343 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 5697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 6437 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 6470 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 799 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 95 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see
-system.physmem.totQLat 4645349999 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9161289999 # Sum of mem lat for all requests
-system.physmem.totBusLat 1121725000 # Total cycles spent in databus access
-system.physmem.totBankLat 3394215000 # Total cycles spent in bank access
-system.physmem.avgQLat 20706.28 # Average queueing delay per request
-system.physmem.avgBankLat 15129.44 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40835.72 # Average memory access latency
-system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.04 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 14.56 # Average write queue length over time
-system.physmem.readRowHits 193479 # Number of row buffer hits during reads
-system.physmem.writeRowHits 105949 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.24 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes
-system.physmem.avgGap 13729510.94 # Average gap between requests
-system.iocache.replacements 47582 # number of replacements
-system.iocache.tagsinuse 0.103934 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47598 # Sample count of references to valid blocks.
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4992018141000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.103934 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.006496 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 917 # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47637 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47637 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47637 # number of overall misses
-system.iocache.overall_misses::total 47637 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144155397 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 144155397 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9929896111 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9929896111 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10074051508 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10074051508 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10074051508 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10074051508 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47637 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47637 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47637 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47637 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157203.268266 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 157203.268266 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212540.584568 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 212540.584568 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 211475.355459 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211475.355459 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 211475.355459 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 131232 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 11911 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.017715 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47637 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47637 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47637 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47637 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96449927 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96449927 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7499098563 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7499098563 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7595548490 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7595548490 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7595548490 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105179.854962 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 105179.854962 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160511.527461 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 160511.527461 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 86228247 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86228247 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1109691 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81322722 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 79235054 # Number of BTB hits
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
+system.physmem.totQLat 2046328821 # Total ticks spent queuing
+system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
+system.physmem.readRowHits 147319 # Number of row buffer hits during reads
+system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
+system.physmem.avgGap 16010977.14 # Average gap between requests
+system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
+system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
+system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.branchPred.lookups 94759510 # Number of BP lookups
+system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.432860 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.numCycles 448477988 # number of cpu cycles simulated
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.numCycles 480891878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27463696 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 426083477 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86228247 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79235054 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163617772 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4719624 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125826 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63227537 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 35895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 53383 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9034836 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 484573 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2662 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 258095876 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.259036 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.417947 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94906138 36.77% 36.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1565225 0.61% 37.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71916844 27.86% 65.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 940016 0.36% 65.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1600383 0.62% 66.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2424857 0.94% 67.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1078498 0.42% 67.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1383259 0.54% 68.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82280656 31.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 258095876 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192269 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950066 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31171664 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60678279 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159406116 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3268443 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3571374 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838032918 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3571374 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33913667 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37519467 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 11021070 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159605851 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12464447 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834371126 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19504 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5869459 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4764277 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 8601 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 995955832 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1811371309 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1811370333 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 976 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964482413 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31473412 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 459237 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 467213 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28827657 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17084902 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10144761 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1200685 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 943086 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 828239567 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1251844 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823277169 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 150176 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22096824 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33604785 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 197691 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 258095876 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.189811 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.384487 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71559419 27.73% 27.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15540861 6.02% 33.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10303423 3.99% 37.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7474044 2.90% 40.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75918752 29.41% 70.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3850758 1.49% 71.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72514611 28.10% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 781198 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 152810 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 258095876 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 369026 34.39% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 552435 51.48% 85.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 151573 14.13% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 311214 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795705202 96.65% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17863780 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9396973 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823277169 # Type of FU issued
-system.cpu.iq.rate 1.835714 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1073034 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001303 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1906003583 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851598062 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818801577 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
+system.cpu.iq.rate 1.759858 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 824038818 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1644527 # Number of loads that had data forwarded from stores
+system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3094800 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23435 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11502 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1720038 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932547 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11959 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3571374 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26260647 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2115726 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829491411 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 321621 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17084902 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10144761 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 719315 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1617594 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12405 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11502 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 654420 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 592576 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1246996 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821399469 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17452724 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1877699 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26617414 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83217280 # Number of branches executed
-system.cpu.iew.exec_stores 9164690 # Number of stores executed
-system.cpu.iew.exec_rate 1.831527 # Inst execution rate
-system.cpu.iew.wb_sent 820937084 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818801671 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639944880 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045797819 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.825734 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611920 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 22903910 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1054151 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1114557 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254524502 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.168565 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.854370 # Number of insts commited each cycle
+system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
+system.cpu.iew.exec_branches 84810471 # Number of branches executed
+system.cpu.iew.exec_stores 9925440 # Number of stores executed
+system.cpu.iew.exec_rate 1.747546 # Inst execution rate
+system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 651539387 # num instructions producing a value
+system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82731188 32.50% 32.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11811542 4.64% 37.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3909670 1.54% 38.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74949600 29.45% 68.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2435927 0.96% 69.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1480813 0.58% 69.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 938860 0.37% 70.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70918382 27.86% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5348520 2.10% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254524502 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407992820 # Number of instructions committed
-system.cpu.commit.committedOps 806477449 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407959263 # Number of instructions committed
+system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22414822 # Number of memory references committed
-system.cpu.commit.loads 13990099 # Number of loads committed
-system.cpu.commit.membars 474403 # Number of memory barriers committed
-system.cpu.commit.branches 82204209 # Number of branches committed
-system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735419466 # Number of committed integer instructions.
-system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5348520 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1078479140 # The number of ROB reads
-system.cpu.rob.rob_writes 1662352652 # The number of ROB writes
-system.cpu.timesIdled 1219186 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 190382112 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9817459293 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407992820 # Number of Instructions Simulated
-system.cpu.committedOps 806477449 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407992820 # Number of Instructions Simulated
-system.cpu.cpi 1.099230 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.099230 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.909728 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.909728 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1507089895 # number of integer regfile reads
-system.cpu.int_regfile_writes 977019847 # number of integer regfile writes
-system.cpu.fp_regfile_reads 94 # number of floating regfile reads
-system.cpu.misc_regfile_reads 264717116 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402314 # number of misc regfile writes
-system.cpu.icache.replacements 1047040 # number of replacements
-system.cpu.icache.tagsinuse 510.337680 # Cycle average of tags in use
-system.cpu.icache.total_refs 7922656 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1047552 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.563019 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 56182186000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.337680 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.996753 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.996753 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7922656 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7922656 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7922656 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7922656 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7922656 # number of overall hits
-system.cpu.icache.overall_hits::total 7922656 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1112177 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1112177 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1112177 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1112177 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1112177 # number of overall misses
-system.cpu.icache.overall_misses::total 1112177 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 15267217991 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 15267217991 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 15267217991 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 15267217991 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 15267217991 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 15267217991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9034833 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9034833 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9034833 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9034833 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9034833 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9034833 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123099 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.123099 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.123099 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.123099 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.123099 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.123099 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.327567 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13727.327567 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13727.327567 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13727.327567 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 9786 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 33.744828 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62286 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 62286 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 62286 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 62286 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 62286 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 62286 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1049891 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1049891 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1049891 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1049891 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1049891 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1049891 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12557489993 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12557489993 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12557489993 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12557489993 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12557489993 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12557489993 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116205 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.116205 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116205 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.116205 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11960.755919 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11960.755919 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11960.755919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11960.755919 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements 9201 # number of replacements
-system.cpu.itb_walker_cache.tagsinuse 6.008096 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 25985 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs 9214 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs 2.820165 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102794236000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008096 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375506 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total 0.375506 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25989 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 25989 # number of ReadReq hits
+system.cpu.commit.refs 22368017 # Number of memory references committed
+system.cpu.commit.loads 13951296 # Number of loads committed
+system.cpu.commit.membars 447981 # Number of memory barriers committed
+system.cpu.commit.branches 82209281 # Number of branches committed
+system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155854 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1325977641 # The number of ROB reads
+system.cpu.rob.rob_writes 1738470998 # The number of ROB writes
+system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407959263 # Number of Instructions Simulated
+system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads
+system.cpu.int_regfile_writes 669949193 # number of integer regfile writes
+system.cpu.fp_regfile_reads 124 # number of floating regfile reads
+system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads
+system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes
+system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads
+system.cpu.misc_regfile_writes 400822 # number of misc regfile writes
+system.cpu.dcache.tags.replacements 1703381 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits
+system.cpu.dcache.overall_hits::total 21312315 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses
+system.cpu.dcache.overall_misses::total 2620606 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 20451778744 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 52129012244 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 52129012244 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 52129012244 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 52129012244 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 15046860 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 15046860 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8407012 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8407012 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 479049 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 479049 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked
+system.cpu.dcache.writebacks::writebacks 1592887 # number of writebacks
+system.cpu.dcache.writebacks::total 1592887 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868287 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 868287 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42120 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 42120 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 910407 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 910407 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 910407 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 910407 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1015040 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1015040 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 287119 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 287119 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 404591 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 404591 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1302159 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1302159 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1706750 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1706750 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 98117221000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 98117221000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 167022.250404 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 167022.250404 # average overall mshr uncacheable latency
+system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency
+system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency
+system.cpu.icache.tags.replacements 1273398 # number of replacements
+system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 14031709 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits
+system.cpu.icache.overall_hits::total 11313989 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses
+system.cpu.icache.overall_misses::total 1443748 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked
+system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks
+system.cpu.icache.writebacks::total 1273398 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency
+system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25991 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 25991 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25991 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 25991 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10086 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 10086 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10086 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 10086 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10086 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 10086 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117807500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117807500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117807500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 117807500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117807500 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 117807500 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36075 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 36075 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36077 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 36077 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36077 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 36077 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.279584 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.279584 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.279569 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.279569 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.279569 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.279569 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11680.299425 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11680.299425 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11680.299425 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11680.299425 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11680.299425 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1386 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1386 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10086 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10086 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10086 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 10086 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10086 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10086 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97635500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97635500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97635500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97635500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97635500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97635500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.279584 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.279584 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.279569 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.279569 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.279569 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9680.299425 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9680.299425 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9680.299425 # average overall mshr miss latency
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 108065 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 12.354963 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 134808 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 108080 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.247298 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5099892629000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.354963 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.772185 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total 0.772185 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134808 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 134808 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134808 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 134808 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134808 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 134808 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109105 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 109105 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109105 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 109105 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109105 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 109105 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1388403500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1388403500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1388403500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 1388403500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1388403500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 1388403500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243913 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 243913 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243913 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 243913 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243913 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 243913 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447311 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447311 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447311 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447311 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447311 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447311 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12725.388387 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12725.388387 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12725.388387 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12725.388387 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12725.388387 # average overall miss latency
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 24362 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 24362 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109105 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109105 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109105 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 109105 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109105 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 109105 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1170193500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1170193500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1170193500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1170193500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447311 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447311 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447311 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447311 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10725.388387 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10725.388387 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10725.388387 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10725.388387 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1660424 # number of replacements
-system.cpu.dcache.tagsinuse 511.994188 # Cycle average of tags in use
-system.cpu.dcache.total_refs 19105277 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1660936 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11.502717 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.994188 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 11003963 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11003963 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8096336 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8096336 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 19100299 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 19100299 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 19100299 # number of overall hits
-system.cpu.dcache.overall_hits::total 19100299 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2241441 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2241441 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 318912 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 318912 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2560353 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2560353 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2560353 # number of overall misses
-system.cpu.dcache.overall_misses::total 2560353 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32061348000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32061348000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9677558995 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9677558995 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 41738906995 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 41738906995 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 41738906995 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 41738906995 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13245404 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13245404 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8415248 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8415248 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21660652 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21660652 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21660652 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21660652 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169224 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.169224 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037897 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.037897 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.118203 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.118203 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.118203 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.118203 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14303.900036 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14303.900036 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30345.546718 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30345.546718 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16302.012650 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16302.012650 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16302.012650 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 390714 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42563 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.179663 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1561895 # number of writebacks
-system.cpu.dcache.writebacks::total 1561895 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868390 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 868390 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26484 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 26484 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 894874 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 894874 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 894874 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 894874 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1373051 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1373051 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292428 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 292428 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1665479 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1665479 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1665479 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1665479 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17447685000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17447685000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8836657995 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8836657995 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26284342995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 26284342995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26284342995 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26284342995 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349027500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349027500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523629000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523629000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99872656500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 99872656500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103662 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103662 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034750 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034750 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076890 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076890 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076890 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.237386 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.237386 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30218.234899 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30218.234899 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15781.851945 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15781.851945 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15781.851945 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15781.851945 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 113316 # number of replacements
-system.cpu.l2cache.tagsinuse 64844.947508 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3926990 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 177399 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 22.136483 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 218233367500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 50081.422465 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 7.214267 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131819 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 3279.773941 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 11476.405015 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.764182 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000110 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.050045 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.175116 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.989455 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 104037 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8366 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1030644 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1335229 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2478276 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1587643 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1587643 # number of Writeback hits
+system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency
+system.cpu.l2cache.tags.replacements 108236 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 48931.543804 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 58.288371 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.037525 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3440.033923 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 12323.035126 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.746636 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000889 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000046 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052491 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.188035 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.988097 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 64158 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2466 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3980 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57082 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978973 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 49981831 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 49981831 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 1631474 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 1631474 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 1270391 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 1270391 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 340 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 340 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 155070 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 155070 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 104037 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 8366 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1030644 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1490299 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2633346 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 104037 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 8366 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1030644 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1490299 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2633346 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16850 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 36755 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 53656 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 3711 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 3711 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133382 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133382 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 16850 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 170137 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 187038 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 16850 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 170137 # number of overall misses
-system.cpu.l2cache.overall_misses::total 187038 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4321500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 844000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1148867000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2499324500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 3653357000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17608000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 17608000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6900952000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6900952000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4321500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 844000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1148867000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9400276500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10554309000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4321500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 844000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1148867000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9400276500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10554309000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 104082 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8372 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1047494 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1371984 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2531932 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1587643 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1587643 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4051 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 4051 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 288452 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 288452 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 104082 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 8372 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1047494 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1660436 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2820384 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 104082 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 8372 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1047494 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1660436 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2820384 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000432 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000717 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016086 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026790 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021192 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916070 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916070 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.462406 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.462406 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000432 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000717 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016086 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102465 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.066317 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000432 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000717 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016086 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102465 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.066317 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 96033.333333 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 140666.666667 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68182.017804 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67999.578289 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68088.508275 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4744.812719 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4744.812719 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51738.255537 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51738.255537 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 96033.333333 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 140666.666667 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68182.017804 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55251.218136 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 56428.688288 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 96033.333333 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 140666.666667 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68182.017804 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55251.218136 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 56428.688288 # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data 157196 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 157196 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1257840 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 1257840 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 140642 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13110 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1380239 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 1533991 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 140642 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 13110 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 1257840 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1537435 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2949027 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 140642 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 13110 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 1257840 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1537435 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2949027 # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1498 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 127805 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 127805 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15982 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 15982 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 124 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 7 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 38662 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 38793 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 15982 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 166467 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 182580 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 15982 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 166467 # number of overall misses
+system.cpu.l2cache.overall_misses::total 182580 # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60579000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 60579000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16318726500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 16318726500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2135667000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 2135667000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 17077500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 945500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5106603500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 5124626500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17077500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 945500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 2135667000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 21425330000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23579020000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17077500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 945500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 2135667000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 21425330000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23579020000 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 1631474 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 1631474 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 1270391 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 1270391 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1838 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1838 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 285001 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 285001 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1273822 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 1273822 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 140766 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13117 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1418901 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1572784 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 140766 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 13117 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 1273822 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1703902 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 3131607 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 140766 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 13117 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1273822 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1703902 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 3131607 # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815016 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815016 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.448437 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.448437 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.012546 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.012546 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000881 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000534 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.027248 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024665 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000881 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000534 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012546 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.097698 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.058302 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000881 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000534 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012546 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.097698 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.058302 # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40439.919893 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40439.919893 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127684.570244 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127684.570244 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 133629.520711 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 133629.520711 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 137721.774194 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135071.428571 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132083.272981 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132101.835383 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 129143.498740 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137721.774194 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135071.428571 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 133629.520711 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128706.169992 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 129143.498740 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 102735 # number of writebacks
-system.cpu.l2cache.writebacks::total 102735 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16849 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36754 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 53654 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3711 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 3711 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133382 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 133382 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 16849 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 170136 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 187036 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 16849 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 170136 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 187036 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3761043 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 768755 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 939262274 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2042484891 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2986276963 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 38121191 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 38121191 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255773881 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255773881 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3761043 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 768755 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 939262274 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7298258772 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8242050844 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3761043 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 768755 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 939262274 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7298258772 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8242050844 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236734500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236734500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2358597000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2358597000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91595331500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91595331500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026789 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021191 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916070 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916070 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462406 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462406 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.066316 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.066316 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55745.876551 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55571.771535 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55658.049036 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10272.484775 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10272.484775 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39403.921676 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39403.921676 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.writebacks::writebacks 98548 # number of writebacks
+system.cpu.l2cache.writebacks::total 98548 # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.dtb.walker 1 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1498 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1498 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127805 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 127805 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15980 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15980 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 123 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 7 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 38662 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 38792 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 123 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 15980 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 166467 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 182577 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 123 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 15980 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 166467 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 182577 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102897000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102897000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15040676500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15040676500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1975642505 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1975642505 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 15740000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 875500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4799287008 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4815902508 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15740000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 875500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1975642505 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19839963508 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 21832221513 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15740000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 875500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1975642505 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19839963508 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 21832221513 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948626000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
+system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 47572 # number of replacements
+system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 428643 # Number of tag accesses
+system.iocache.tags.data_accesses 428643 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
+system.iocache.overall_misses::total 47627 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.membus.trans_dist::ReadReq 573476 # Transaction distribution
+system.membus.trans_dist::ReadResp 628544 # Transaction distribution
+system.membus.trans_dist::WriteReq 13974 # Transaction distribution
+system.membus.trans_dist::WriteResp 13974 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution
+system.membus.trans_dist::CleanEvict 10528 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 20 # Transaction distribution
+system.membus.trans_dist::ReadExReq 127539 # Transaction distribution
+system.membus.trans_dist::ReadExResp 127538 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution
+system.membus.trans_dist::MessageReq 1666 # Transaction distribution
+system.membus.trans_dist::MessageResp 1666 # Transaction distribution
+system.membus.trans_dist::BadAddressError 611 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1549 # Total snoops (count)
+system.membus.snoop_fanout::samples 976982 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram
+system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 976982 # Request fanout histogram
+system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
projects / gem5.git / blobdiff