---------- Begin Simulation Statistics ----------
-sim_seconds 5.133763 # Number of seconds simulated
-sim_ticks 5133762710000 # Number of ticks simulated
-final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.230834 # Number of seconds simulated
+sim_ticks 5230834315000 # Number of ticks simulated
+final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156198 # Simulator instruction rate (inst/s)
-host_op_rate 308758 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1966557914 # Simulator tick rate (ticks/s)
-host_mem_usage 728732 # Number of bytes of host memory used
-host_seconds 2610.53 # Real time elapsed on the host
-sim_insts 407759186 # Number of instructions simulated
-sim_ops 806023868 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1025408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10767936 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14241664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1025408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1025408 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9508160 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9508160 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38188 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16022 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168249 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 222526 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 148565 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 148565 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 476070 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 773 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 199738 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2097474 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2774118 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 199738 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 199738 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1852084 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1852084 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1852084 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 476070 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 773 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 222526 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 148565 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 222526 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 148565 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 14241664 # Total number of bytes read from memory
-system.physmem.bytesWritten 9508160 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 75 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 14393 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 13573 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13866 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13628 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13175 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 13794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13878 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 13620 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13949 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 13975 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 14441 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 14348 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 14346 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 13392 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9773 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 9207 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 9622 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 9014 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 9405 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 9183 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8703 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 9254 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 9156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 9367 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 9240 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 9684 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 9527 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 9658 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 8799 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5133762656000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 222526 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 148565 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 174531 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 21417 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 7486 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2970 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2509 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2070 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1259 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1043 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 993 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 934 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 896 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 849 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 939 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 711 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 498 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 225 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 146 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+host_inst_rate 207627 # Simulator instruction rate (inst/s)
+host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
+host_mem_usage 751184 # Number of bytes of host memory used
+host_seconds 1964.86 # Real time elapsed on the host
+sim_insts 407959263 # Number of instructions simulated
+sim_ops 806441023 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory
+system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 181488 # Number of read requests accepted
+system.physmem.writeReqs 145215 # Number of write requests accepted
+system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11156 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11363 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11879 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11399 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11231 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10765 # Per bank write bursts
+system.physmem.perBankRdBursts::6 10426 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10967 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10953 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10767 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11374 # Per bank write bursts
+system.physmem.perBankRdBursts::11 11178 # Per bank write bursts
+system.physmem.perBankRdBursts::12 12058 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12613 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11821 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11247 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9305 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9167 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9550 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8690 # Per bank write bursts
+system.physmem.perBankWrBursts::4 9047 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8729 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8333 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8814 # Per bank write bursts
+system.physmem.perBankWrBursts::8 9019 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9026 # Per bank write bursts
+system.physmem.perBankWrBursts::10 9076 # Per bank write bursts
+system.physmem.perBankWrBursts::11 9210 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9034 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9699 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9456 # Per bank write bursts
+system.physmem.perBankWrBursts::15 9034 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 5230834265500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 181488 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 145215 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 5408 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 5706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 6402 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 6442 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 6450 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 6452 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 6453 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 6454 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6453 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 62801 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 377.966975 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 153.936826 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 1272.632195 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67 27908 44.44% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131 9784 15.58% 60.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195 5938 9.46% 69.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259 3957 6.30% 75.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323 2545 4.05% 79.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387 2018 3.21% 83.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451 1524 2.43% 85.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515 1187 1.89% 87.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579 1022 1.63% 88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643 897 1.43% 90.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707 594 0.95% 91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771 559 0.89% 92.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835 423 0.67% 92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899 383 0.61% 93.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963 375 0.60% 94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027 421 0.67% 94.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091 292 0.46% 95.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155 205 0.33% 95.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283 163 0.26% 96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347 146 0.23% 96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411 144 0.23% 96.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475 476 0.76% 97.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539 183 0.29% 97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603 124 0.20% 97.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667 88 0.14% 97.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731 60 0.10% 98.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795 51 0.08% 98.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859 42 0.07% 98.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923 29 0.05% 98.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987 32 0.05% 98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051 30 0.05% 98.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179 17 0.03% 98.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243 11 0.02% 98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307 16 0.03% 98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563 13 0.02% 98.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627 7 0.01% 98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755 8 0.01% 98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819 3 0.00% 98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947 6 0.01% 98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075 6 0.01% 98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203 8 0.01% 98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267 4 0.01% 98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395 8 0.01% 98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587 4 0.01% 98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651 2 0.00% 98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715 3 0.00% 98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779 8 0.01% 98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099 27 0.04% 98.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227 3 0.00% 98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419 4 0.01% 98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739 3 0.00% 98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995 3 0.00% 98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123 8 0.01% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891 3 0.00% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659 2 0.00% 98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851 1 0.00% 98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6979 3 0.00% 98.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427 3 0.00% 98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555 3 0.00% 98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875 4 0.01% 98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939 2 0.00% 98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539 10 0.02% 99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10371 2 0.00% 99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10627 3 0.00% 99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11267 2 0.00% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315 2 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14083 2 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14467 2 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14787 3 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915 33 0.05% 99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043 11 0.02% 99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107 12 0.02% 99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235 9 0.01% 99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363 8 0.01% 99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15683 3 0.00% 99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15747 7 0.01% 99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067 10 0.02% 99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16131 5 0.01% 99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259 6 0.01% 99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16320-16323 10 0.02% 99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387 63 0.10% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16576-16579 2 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16643 2 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18368-18371 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62801 # Bytes accessed per row activation
-system.physmem.totQLat 4020206249 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 8301079999 # Sum of mem lat for all requests
-system.physmem.totBusLat 1112255000 # Total cycles spent in databus access
-system.physmem.totBankLat 3168618750 # Total cycles spent in bank access
-system.physmem.avgQLat 18072.32 # Average queueing delay per request
-system.physmem.avgBankLat 14244.12 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 37316.44 # Average memory access latency
-system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.04 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 13.16 # Average write queue length over time
-system.physmem.readRowHits 198897 # Number of row buffer hits during reads
-system.physmem.writeRowHits 109310 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.41 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes
-system.physmem.avgGap 13834241.89 # Average gap between requests
-system.membus.throughput 5102506 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 662304 # Transaction distribution
-system.membus.trans_dist::ReadResp 662304 # Transaction distribution
-system.membus.trans_dist::WriteReq 13698 # Transaction distribution
-system.membus.trans_dist::WriteResp 13698 # Transaction distribution
-system.membus.trans_dist::Writeback 148565 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2229 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1751 # Transaction distribution
-system.membus.trans_dist::ReadExReq 179560 # Transaction distribution
-system.membus.trans_dist::ReadExResp 179558 # Transaction distribution
-system.membus.trans_dist::MessageReq 1642 # Transaction distribution
-system.membus.trans_dist::MessageResp 1642 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 25548207 # Total data (bytes)
-system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 250293000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583289000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1608355497 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3156883661 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47574 # number of replacements
-system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
-system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses
-system.iocache.overall_misses::total 47629 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151796185 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 151796185 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10322328602 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10322328602 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10474124787 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10474124787 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10474124787 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10474124787 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 166992.502750 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 220940.252611 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 219910.659199 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 219910.659199 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 148616 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 13635 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.899597 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 46667 # number of writebacks
-system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104494685 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 104494685 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7891444112 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7891444112 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7995938797 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7995938797 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.throughput 638140 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 225493 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225493 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57527 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57527 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1642 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1642 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 3276058 # Total data (bytes)
-system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 424430792 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 53423005 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.branchPred.lookups 85618831 # Number of BP lookups
-system.cpu.branchPred.condPredicted 85618831 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 881906 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 79126559 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 77540225 # Number of BTB hits
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
+system.physmem.totQLat 2046328821 # Total ticks spent queuing
+system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
+system.physmem.readRowHits 147319 # Number of row buffer hits during reads
+system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
+system.physmem.avgGap 16010977.14 # Average gap between requests
+system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
+system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
+system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.branchPred.lookups 94759510 # Number of BP lookups
+system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.995194 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1441540 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 180626 # Number of incorrect RAS predictions.
-system.cpu.numCycles 453839632 # number of cpu cycles simulated
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.numCycles 480891878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 25514423 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 422776164 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85618831 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 78981765 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 162666633 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3997481 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 100403 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 71304729 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 44393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94570 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8483452 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 380361 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2201 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 262796476 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.177336 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.411374 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 100544783 38.26% 38.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1535684 0.58% 38.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71830288 27.33% 66.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 894888 0.34% 66.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1570094 0.60% 67.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2394528 0.91% 68.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1014297 0.39% 68.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1322217 0.50% 68.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81689697 31.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 262796476 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.188654 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.931554 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29415381 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 68460720 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158509709 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3339560 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3071106 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 832655242 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 935 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3071106 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 32114015 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 43120028 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 12611794 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158799152 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13080381 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 829727330 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21673 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6047730 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5146675 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 9377 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 991375726 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1800594508 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1800594068 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 440 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 963942859 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27432865 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 453030 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 459006 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 29568179 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 16736842 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 9827220 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1098890 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 921986 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 824947174 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1184809 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 820992991 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 145624 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19292542 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 29357019 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 130694 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 262796476 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.124064 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.400943 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 76438982 29.09% 29.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15751400 5.99% 35.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10538627 4.01% 39.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7358771 2.80% 41.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75737390 28.82% 70.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3750331 1.43% 72.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72306613 27.51% 99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 767765 0.29% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 146597 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 262796476 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 351017 33.38% 33.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 1 0.00% 33.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 348 0.03% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 547344 52.04% 85.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 152992 14.55% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 308184 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 793508376 96.65% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 149615 0.02% 96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 124401 0.02% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17677574 2.15% 98.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9224841 1.12% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 820992991 # Type of FU issued
-system.cpu.iq.rate 1.808994 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1051702 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1906088677 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 845434927 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 817071068 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 189 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 821736420 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 89 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1694381 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
+system.cpu.iq.rate 1.759858 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2750139 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 17720 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12102 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1408836 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1931381 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 12080 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3071106 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 31257120 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2152669 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 826131983 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 242676 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 16736842 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 9827220 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 690491 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1620064 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 13028 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12102 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 497258 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 506632 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1003890 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 819577252 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17369785 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1415738 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26409608 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83098710 # Number of branches executed
-system.cpu.iew.exec_stores 9039823 # Number of stores executed
-system.cpu.iew.exec_rate 1.805874 # Inst execution rate
-system.cpu.iew.wb_sent 819172462 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 817071124 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 638600161 # num instructions producing a value
-system.cpu.iew.wb_consumers 1043929120 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.800352 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 19998846 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1054115 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 892238 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 259725370 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.103370 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.863932 # Number of insts commited each cycle
+system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
+system.cpu.iew.exec_branches 84810471 # Number of branches executed
+system.cpu.iew.exec_stores 9925440 # Number of stores executed
+system.cpu.iew.exec_rate 1.747546 # Inst execution rate
+system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 651539387 # num instructions producing a value
+system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 88203628 33.96% 33.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11848657 4.56% 38.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3832219 1.48% 40.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74739253 28.78% 68.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2381920 0.92% 69.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1474779 0.57% 70.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 859132 0.33% 70.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70849609 27.28% 97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5536173 2.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 259725370 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407759186 # Number of instructions committed
-system.cpu.commit.committedOps 806023868 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407959263 # Number of instructions committed
+system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22405086 # Number of memory references committed
-system.cpu.commit.loads 13986702 # Number of loads committed
-system.cpu.commit.membars 474409 # Number of memory barriers committed
-system.cpu.commit.branches 82159690 # Number of branches committed
-system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735008844 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1154896 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5536173 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1080133651 # The number of ROB reads
-system.cpu.rob.rob_writes 1655131261 # The number of ROB writes
-system.cpu.timesIdled 1259877 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 191043156 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9813691352 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407759186 # Number of Instructions Simulated
-system.cpu.committedOps 806023868 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407759186 # Number of Instructions Simulated
-system.cpu.cpi 1.113009 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.113009 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.898465 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.898465 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1504423855 # number of integer regfile reads
-system.cpu.int_regfile_writes 975340027 # number of integer regfile writes
-system.cpu.fp_regfile_reads 56 # number of floating regfile reads
-system.cpu.misc_regfile_reads 264091330 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402284 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 53596956 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 3010019 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3009469 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13698 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13698 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1583020 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1906694 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6122854 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 16266 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154977 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8200791 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61010496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207591623 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 510912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5512832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 274625863 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 552000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1434043234 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3142652791 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 12430241 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 952820 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7477461 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7477461 # number of overall hits
-system.cpu.icache.overall_hits::total 7477461 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1005989 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1005989 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1005989 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1005989 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1005989 # number of overall misses
-system.cpu.icache.overall_misses::total 1005989 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232079935 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14232079935 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14232079935 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14232079935 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14232079935 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14232079935 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8483450 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8483450 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8483450 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8483450 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8483450 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8483450 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118583 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.118583 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.118583 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.118583 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.118583 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.118583 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14147.351447 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14147.351447 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 174 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 35.580460 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52584 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 52584 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 52584 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 52584 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 52584 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 52584 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953405 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 953405 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 953405 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 953405 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 953405 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 953405 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11737352011 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11737352011 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11737352011 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11737352011 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11737352011 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11737352011 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112384 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.112384 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.112384 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.375429 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21911 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 21911 # number of ReadReq hits
+system.cpu.commit.refs 22368017 # Number of memory references committed
+system.cpu.commit.loads 13951296 # Number of loads committed
+system.cpu.commit.membars 447981 # Number of memory barriers committed
+system.cpu.commit.branches 82209281 # Number of branches committed
+system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155854 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction
+system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1325977641 # The number of ROB reads
+system.cpu.rob.rob_writes 1738470998 # The number of ROB writes
+system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407959263 # Number of Instructions Simulated
+system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads
+system.cpu.int_regfile_writes 669949193 # number of integer regfile writes
+system.cpu.fp_regfile_reads 124 # number of floating regfile reads
+system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads
+system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes
+system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads
+system.cpu.misc_regfile_writes 400822 # number of misc regfile writes
+system.cpu.dcache.tags.replacements 1703381 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits
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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 713808442 # number of ReadReq MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 713808442 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 713808442 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency
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-system.cpu.dcache.overall_miss_latency::total 45345021971 # number of overall miss cycles
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 17767.541337 # average overall miss latency
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13093.178796 # average ReadReq mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
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+system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
+system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 47572 # number of replacements
+system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 428643 # Number of tag accesses
+system.iocache.tags.data_accesses 428643 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
+system.iocache.overall_misses::total 47627 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.membus.trans_dist::ReadReq 573476 # Transaction distribution
+system.membus.trans_dist::ReadResp 628544 # Transaction distribution
+system.membus.trans_dist::WriteReq 13974 # Transaction distribution
+system.membus.trans_dist::WriteResp 13974 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution
+system.membus.trans_dist::CleanEvict 10528 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 20 # Transaction distribution
+system.membus.trans_dist::ReadExReq 127539 # Transaction distribution
+system.membus.trans_dist::ReadExResp 127538 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution
+system.membus.trans_dist::MessageReq 1666 # Transaction distribution
+system.membus.trans_dist::MessageResp 1666 # Transaction distribution
+system.membus.trans_dist::BadAddressError 611 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1549 # Total snoops (count)
+system.membus.snoop_fanout::samples 976982 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram
+system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 976982 # Request fanout histogram
+system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
projects / gem5.git / blobdiff