---------- Begin Simulation Statistics ----------
-sim_seconds 5.125902 # Number of seconds simulated
-sim_ticks 5125902116500 # Number of ticks simulated
-final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.230834 # Number of seconds simulated
+sim_ticks 5230834315000 # Number of ticks simulated
+final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196886 # Simulator instruction rate (inst/s)
-host_op_rate 389187 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2473535129 # Simulator tick rate (ticks/s)
-host_mem_usage 743248 # Number of bytes of host memory used
-host_seconds 2072.30 # Real time elapsed on the host
-sim_insts 408006726 # Number of instructions simulated
-sim_ops 806511598 # Number of ops (including micro ops) simulated
+host_inst_rate 207627 # Simulator instruction rate (inst/s)
+host_op_rate 410431 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2662189440 # Simulator tick rate (ticks/s)
+host_mem_usage 751184 # Number of bytes of host memory used
+host_seconds 1964.86 # Real time elapsed on the host
+sim_insts 407959263 # Number of instructions simulated
+sim_ops 806441023 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
-system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1288465 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 185800 # Number of read requests accepted
-system.physmem.writeReqs 149916 # Number of write requests accepted
-system.physmem.readBursts 185800 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 149916 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11876224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 14976 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9592960 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11891200 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9594624 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 234 # Number of DRAM read bursts serviced by the write queue
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+system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory
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+system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 181488 # Number of read requests accepted
+system.physmem.writeReqs 145215 # Number of write requests accepted
+system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1736 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11489 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10946 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
-system.physmem.totGap 5125902065000 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
+system.physmem.totGap 5230834265500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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+system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 72846 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 294.719271 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.256286 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 318.919065 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 28471 39.08% 39.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17446 23.95% 63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7310 10.03% 73.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 4243 5.82% 78.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2987 4.10% 82.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1984 2.72% 85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1403 1.93% 87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1126 1.55% 89.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7876 10.81% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 72846 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7377 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.152094 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 560.212559 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 7376 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7377 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7377 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.318558 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.615023 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 12.539295 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 6330 85.81% 85.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 64 0.87% 86.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 33 0.45% 87.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 268 3.63% 90.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 287 3.89% 94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 24 0.33% 94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 24 0.33% 95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 16 0.22% 95.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 20 0.27% 95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.03% 95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 6 0.08% 95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 2 0.03% 95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 237 3.21% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 3 0.04% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.03% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 11 0.15% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 12 0.16% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.04% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 6 0.08% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 3 0.04% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 13 0.18% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7377 # Writes before turning the bus around for reads
-system.physmem.totQLat 2068154250 # Total ticks spent queuing
-system.physmem.totMemAccLat 5547516750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 927830000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11145.11 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads
+system.physmem.totQLat 2046328821 # Total ticks spent queuing
+system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29895.11 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.36 # Average write queue length when enqueuing
-system.physmem.readRowHits 151753 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110856 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes
-system.physmem.avgGap 15268566.48 # Average gap between requests
-system.physmem.pageHitRate 78.28 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4919748958000 # Time in different power states
-system.physmem.memoryStateTime::REF 171165020000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 34988035500 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 267185520 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 283530240 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 145785750 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 154704000 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 715946400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 731460600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 477984240 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 493302960 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 334798779120 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 334798779120 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 129305495790 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 129519356940 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 2962113436500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 2961925839000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3427824613320 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
-system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 662592 # Transaction distribution
-system.membus.trans_dist::ReadResp 662582 # Transaction distribution
-system.membus.trans_dist::WriteReq 13889 # Transaction distribution
-system.membus.trans_dist::WriteResp 13889 # Transaction distribution
-system.membus.trans_dist::Writeback 103196 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
-system.membus.trans_dist::MessageReq 1644 # Transaction distribution
-system.membus.trans_dist::MessageResp 1644 # Transaction distribution
-system.membus.trans_dist::BadAddressError 10 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 949 # Total snoops (count)
-system.membus.snoop_fanout::samples 338415 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 338415 # Request fanout histogram
-system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47575 # number of replacements
-system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428670 # Number of tag accesses
-system.iocache.tags.data_accesses 428670 # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
-system.iocache.demand_misses::total 910 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
-system.iocache.overall_misses::total 910 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 46720 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 86911006 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80066722 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78189070 # Number of BTB hits
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing
+system.physmem.readRowHits 147319 # Number of row buffer hits during reads
+system.physmem.writeRowHits 107244 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes
+system.physmem.avgGap 16010977.14 # Average gap between requests
+system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.813765 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states
+system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.831291 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states
+system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.cpu.branchPred.lookups 94759510 # Number of BP lookups
+system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 449563158 # number of cpu cycles simulated
+system.cpu.numCycles 480891878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27553144 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 429142218 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86911006 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79745348 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 417985667 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1891240 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 143316 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 50930 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 210883 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 127962 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 502 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9183903 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 446388 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4881 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 447018024 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.894555 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.051977 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 281457902 62.96% 62.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2285728 0.51% 63.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72178245 16.15% 79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1597297 0.36% 79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2150673 0.48% 80.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2329203 0.52% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1531441 0.34% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1871505 0.42% 81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81616030 18.26% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 447018024 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.193323 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.954576 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 22975502 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 264891753 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150781344 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7423805 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 945620 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838588132 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 945620 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25820685 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 223318475 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13301995 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154670533 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 28960716 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 835102889 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 477440 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12397064 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 181319 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 13705397 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997542850 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1813799496 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1115056771 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 257 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964533940 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33008908 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 469072 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 473209 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 39003947 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17327061 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10187947 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1305152 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1075480 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829577981 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1211612 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824337261 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 238496 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23343623 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36066463 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 155823 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 447018024 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.844081 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.418172 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 262761301 58.78% 58.78% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 10080748 2.26% 64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6920312 1.55% 65.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74355494 16.63% 82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4460813 1.00% 83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72820654 16.29% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1197568 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 565822 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 447018024 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1976611 71.80% 71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 212 0.01% 71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 1052 0.04% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 614146 22.31% 94.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 161054 5.85% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 292817 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795957786 96.56% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150640 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125262 0.02% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18413325 2.23% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9397431 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824337261 # Type of FU issued
-system.cpu.iq.rate 1.833641 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2753075 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003340 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2098683900 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854145561 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819784123 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 216 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 406 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826797417 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1878905 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued
+system.cpu.iq.rate 1.759858 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3325389 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14284 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14518 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1760345 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2224613 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 71287 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 945620 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205593402 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9425350 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 830789593 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 184731 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17327061 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10187947 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 714336 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 416093 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1477345 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27187593 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83308581 # Number of branches executed
-system.cpu.iew.exec_stores 9169768 # Number of stores executed
-system.cpu.iew.exec_rate 1.830056 # Inst execution rate
-system.cpu.iew.wb_sent 822221777 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819784184 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 641108962 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050701242 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.823513 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610172 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24183935 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1055789 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 913678 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 443381671 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.819001 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.675688 # Number of insts commited each cycle
+system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed
+system.cpu.iew.exec_branches 84810471 # Number of branches executed
+system.cpu.iew.exec_stores 9925440 # Number of stores executed
+system.cpu.iew.exec_rate 1.747546 # Inst execution rate
+system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 651539387 # num instructions producing a value
+system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 272578077 61.48% 61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11201647 2.53% 64.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3542666 0.80% 64.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74562549 16.82% 81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2432578 0.55% 82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1609465 0.36% 82.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 914477 0.21% 82.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71049223 16.02% 98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5490989 1.24% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 443381671 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 408006726 # Number of instructions committed
-system.cpu.commit.committedOps 806511598 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407959263 # Number of instructions committed
+system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22429273 # Number of memory references committed
-system.cpu.commit.loads 14001671 # Number of loads committed
-system.cpu.commit.membars 475333 # Number of memory barriers committed
-system.cpu.commit.branches 82207365 # Number of branches committed
-system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735317995 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1155841 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 174216 0.02% 0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 783641693 97.16% 97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 144853 0.02% 97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 121563 0.02% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 14001671 1.74% 98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 8427602 1.04% 100.00% # Class of committed instruction
+system.cpu.commit.refs 22368017 # Number of memory references committed
+system.cpu.commit.loads 13951296 # Number of loads committed
+system.cpu.commit.membars 447981 # Number of memory barriers committed
+system.cpu.commit.branches 82209281 # Number of branches committed
+system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 735219945 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1155854 # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 806511598 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5490989 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1268507964 # The number of ROB reads
-system.cpu.rob.rob_writes 1665044622 # The number of ROB writes
-system.cpu.timesIdled 294262 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 2545134 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9802241311 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 408006726 # Number of Instructions Simulated
-system.cpu.committedOps 806511598 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.101852 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.101852 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.907563 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.907563 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1092659743 # number of integer regfile reads
-system.cpu.int_regfile_writes 656162059 # number of integer regfile writes
-system.cpu.fp_regfile_reads 61 # number of floating regfile reads
-system.cpu.cc_regfile_reads 416306470 # number of cc regfile reads
-system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
-system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
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+system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles
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+system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses)
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system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
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-system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
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-system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
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-system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
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-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses
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+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
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+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
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-system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
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-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
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-system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
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-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
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-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
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-system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
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-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
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-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
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-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits
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-system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits
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-system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 19128334 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses
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-system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses
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-system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses
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-system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 2535648 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses
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-system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10077954292 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 11133204292 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5579000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 473000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1049198000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10077954292 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 11133204292 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275584000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275584000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397149000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397149000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672733000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026176 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021364 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823731 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823731 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464684 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464684 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for demand accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001093 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000560 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016394 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102118 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.067919 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948626000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90948626000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90948626000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 154819.348030 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 154819.348030 # average overall mshr uncacheable latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 217979 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 212035 # Transaction distribution
+system.iobus.trans_dist::ReadResp 212035 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57756 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57756 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1666 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1666 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 47572 # number of replacements
+system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 428643 # Number of tag accesses
+system.iocache.tags.data_accesses 428643 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
+system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses
+system.iocache.overall_misses::total 47627 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 6019105318 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 6019105318 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 6019105318 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 6019105318 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126380.106200 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126380.106200 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3635845639 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3635845639 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 3635845639 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76340.009637 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76340.009637 # average overall mshr miss latency
+system.membus.trans_dist::ReadReq 573476 # Transaction distribution
+system.membus.trans_dist::ReadResp 628544 # Transaction distribution
+system.membus.trans_dist::WriteReq 13974 # Transaction distribution
+system.membus.trans_dist::WriteResp 13974 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution
+system.membus.trans_dist::CleanEvict 10528 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 20 # Transaction distribution
+system.membus.trans_dist::ReadExReq 127539 # Transaction distribution
+system.membus.trans_dist::ReadExResp 127538 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution
+system.membus.trans_dist::MessageReq 1666 # Transaction distribution
+system.membus.trans_dist::MessageResp 1666 # Transaction distribution
+system.membus.trans_dist::BadAddressError 611 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1549 # Total snoops (count)
+system.membus.snoop_fanout::samples 976982 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram
+system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 976982 # Request fanout histogram
+system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
projects / gem5.git / blobdiff