---------- Begin Simulation Statistics ----------
-sim_seconds 5.221365 # Number of seconds simulated
-sim_ticks 5221365015000 # Number of ticks simulated
-final_tick 5221365015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.220167 # Number of seconds simulated
+sim_ticks 5220166723500 # Number of ticks simulated
+final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 248453 # Simulator instruction rate (inst/s)
-host_op_rate 482434 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8587928983 # Simulator tick rate (ticks/s)
-host_mem_usage 826144 # Number of bytes of host memory used
-host_seconds 607.99 # Real time elapsed on the host
-sim_insts 151056354 # Number of instructions simulated
-sim_ops 293314765 # Number of ops (including micro ops) simulated
+host_inst_rate 281505 # Simulator instruction rate (inst/s)
+host_op_rate 546613 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9727443238 # Simulator tick rate (ticks/s)
+host_mem_usage 784792 # Number of bytes of host memory used
+host_seconds 536.64 # Real time elapsed on the host
+sim_insts 151067812 # Number of instructions simulated
+sim_ops 293336428 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11629312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 11629312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9426176 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 9426176 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 181708 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 181708 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 147284 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 147284 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 2227255 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 2227255 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805309 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1805309 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 4032564 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 4032564 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 181708 # Number of read requests accepted
-system.mem_ctrls.writeReqs 147284 # Number of write requests accepted
-system.mem_ctrls.readBursts 181708 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 147284 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 11602944 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 26368 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 9422144 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 11629312 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 9426176 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 412 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11621312 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 11621312 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9422976 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 9422976 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 181583 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 181583 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 147234 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 147234 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 2226234 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 2226234 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805110 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1805110 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 4031344 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 4031344 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 181583 # Number of read requests accepted
+system.mem_ctrls.writeReqs 147234 # Number of write requests accepted
+system.mem_ctrls.readBursts 181583 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 147234 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 11591808 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 29504 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 9419008 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 11621312 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 9422976 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 11315 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 10810 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 10914 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 11597 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 11232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 10763 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 11930 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 10887 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 12498 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 12229 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 11811 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 12012 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 11054 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 10768 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 10809 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 10667 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 10064 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 9276 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 8835 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 9280 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 9017 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 9023 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 9283 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 11329 # Per bank write bursts
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+system.mem_ctrls.perBankRdBursts::15 10613 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 10067 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 9205 # Per bank write bursts
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+system.mem_ctrls.perBankWrBursts::4 9038 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::7 8385 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 9360 # Per bank write bursts
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-system.mem_ctrls.perBankWrBursts::10 9168 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 9776 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 9055 # Per bank write bursts
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-system.mem_ctrls.perBankWrBursts::15 8846 # Per bank write bursts
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+system.mem_ctrls.perBankWrBursts::11 9790 # Per bank write bursts
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+system.mem_ctrls.perBankWrBursts::13 9097 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 9389 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 8917 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 5221364905500 # Total gap between requests
+system.mem_ctrls.totGap 5220166614000 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 181708 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 181583 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 147284 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 181190 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 106 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 147234 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 181021 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 59927 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 350.843927 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 206.536657 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 350.281857 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 19886 33.18% 33.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 13813 23.05% 56.23% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 6078 10.14% 66.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3680 6.14% 72.52% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 2560 4.27% 76.79% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2039 3.40% 80.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1649 2.75% 82.94% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1406 2.35% 85.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 8816 14.71% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 59927 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 8212 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 22.072577 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 311.491456 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023 8206 99.93% 99.93% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples 59923 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 350.629174 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 206.226666 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 350.561474 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 19936 33.27% 33.27% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 13794 23.02% 56.29% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 6108 10.19% 66.48% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 3634 6.06% 72.55% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2579 4.30% 76.85% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 1995 3.33% 80.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1624 2.71% 82.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1412 2.36% 85.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 8841 14.75% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 59923 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 8207 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 22.065919 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 311.578267 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-1023 8201 99.93% 99.93% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 8212 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 8212 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.927545 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.596423 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 3.937922 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 6145 74.83% 74.83% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 16 0.19% 75.02% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 149 1.81% 76.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 20 0.24% 77.08% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 39 0.47% 77.56% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 481 5.86% 83.41% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 195 2.37% 85.79% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 59 0.72% 86.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 612 7.45% 93.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 113 1.38% 95.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 6 0.07% 95.41% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.57% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 284 3.46% 99.03% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.07% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 6 0.07% 99.15% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.20% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.28% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.35% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35 1 0.01% 99.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36 6 0.07% 99.44% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.49% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::38 2 0.02% 99.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::39 6 0.07% 99.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40 1 0.01% 99.60% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41 8 0.10% 99.70% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43 2 0.02% 99.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44 6 0.07% 99.83% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.94% # Writes before turning the bus around for reads
+system.mem_ctrls.rdPerTurnAround::total 8207 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 8207 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17.932497 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 17.599692 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 3.953739 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 6146 74.89% 74.89% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 20 0.24% 75.13% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 127 1.55% 76.68% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 26 0.32% 77.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 39 0.48% 77.47% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21 486 5.92% 83.39% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22 193 2.35% 85.74% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24 617 7.52% 93.97% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25 104 1.27% 95.24% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26 8 0.10% 95.33% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27 15 0.18% 95.52% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28 293 3.57% 99.09% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.13% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30 1 0.01% 99.15% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::31 3 0.04% 99.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32 10 0.12% 99.31% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::34 2 0.02% 99.39% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::35 2 0.02% 99.42% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::36 5 0.06% 99.48% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.49% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::38 5 0.06% 99.55% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::39 2 0.02% 99.57% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.61% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::41 5 0.06% 99.67% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::42 2 0.02% 99.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.73% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::44 3 0.04% 99.77% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::45 5 0.06% 99.83% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::46 2 0.02% 99.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.87% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::49 2 0.02% 99.94% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 8212 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 1926712996 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 5326012996 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 906480000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 10627.44 # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::total 8207 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 1926054246 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 5322091746 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 905610000 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 10634.02 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 29377.44 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgMemAccLat 29384.02 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.95 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 146991 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 121598 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.08 # Row buffer hit rate for reads
+system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 146815 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 121555 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 81.06 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 15870795.96 # Average gap between requests
-system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 221946480 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 121101750 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 697686600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 474096240 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 139619979810 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 3010341298500 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 3492509834100 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 668.889138 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5007866146000 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 174352620000 # Time in different power states
+system.mem_ctrls.avgGap 15875598.32 # Average gap between requests
+system.mem_ctrls.pageHitRate 81.74 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 222014520 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 121138875 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 696781800 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 474647040 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 139500530325 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 3009726629250 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 3491697148290 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 668.887101 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5006844557250 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 174312580000 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 39146148500 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 39009485750 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 231101640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 126097125 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 716414400 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 479895840 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 139466264490 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3010476136500 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3492529634715 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 668.892930 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5008078591499 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 174352620000 # Time in different power states
+system.mem_ctrls_1.actEnergy 231003360 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 126043500 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 715962000 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 479027520 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 139411599210 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 3009804639000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 3491723681070 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 668.892184 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5006961679500 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 174312580000 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 38927077251 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 38884946750 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10442730030 # number of cpu cycles simulated
+system.cpu0.numCycles 10440333447 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.committedInsts 100536790 # Number of instructions committed
-system.cpu0.committedOps 194797787 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 182088702 # Number of integer alu accesses
+system.cpu0.committedInsts 100619599 # Number of instructions committed
+system.cpu0.committedOps 194912227 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 182208047 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu0.num_func_calls 1786032 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 17861740 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 182088702 # number of integer instructions
+system.cpu0.num_func_calls 1789060 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 17876463 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 182208047 # number of integer instructions
system.cpu0.num_fp_insts 48 # number of float instructions
-system.cpu0.num_int_register_reads 340614933 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 155369927 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 340866599 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 155423898 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 104545094 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 75102328 # number of times the CC registers were written
-system.cpu0.num_mem_refs 18441277 # number of memory refs
-system.cpu0.num_load_insts 11598406 # Number of load instructions
-system.cpu0.num_store_insts 6842871 # Number of store instructions
-system.cpu0.num_idle_cycles 9945203438.030096 # Number of idle cycles
-system.cpu0.num_busy_cycles 497526591.969905 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.047643 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.952357 # Percentage of idle cycles
-system.cpu0.Branches 20259437 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 186593 0.10% 0.10% # Class of executed instruction
-system.cpu0.op_class::IntAlu 175972173 90.34% 90.43% # Class of executed instruction
-system.cpu0.op_class::IntMult 117562 0.06% 90.49% # Class of executed instruction
-system.cpu0.op_class::IntDiv 85263 0.04% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 16 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::MemRead 11594262 5.95% 96.49% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6842871 3.51% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 104641558 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 75150612 # number of times the CC registers were written
+system.cpu0.num_mem_refs 18466644 # number of memory refs
+system.cpu0.num_load_insts 11577076 # Number of load instructions
+system.cpu0.num_store_insts 6889568 # Number of store instructions
+system.cpu0.num_idle_cycles 9942379374.520096 # Number of idle cycles
+system.cpu0.num_busy_cycles 497954072.479905 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.047695 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.952305 # Percentage of idle cycles
+system.cpu0.Branches 20277624 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 187137 0.10% 0.10% # Class of executed instruction
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+system.cpu0.op_class::FloatMult 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdMisc 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdSqrt 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.53% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 194798740 # Class of executed instruction
+system.cpu0.op_class::total 194913158 # Class of executed instruction
system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu1.numCycles 10442397548 # number of cpu cycles simulated
+system.cpu1.numCycles 10439192066 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 50519564 # Number of instructions committed
-system.cpu1.committedOps 98516978 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 91922994 # Number of integer alu accesses
+system.cpu1.committedInsts 50448213 # Number of instructions committed
+system.cpu1.committedOps 98424201 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 91824874 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu1.num_func_calls 994306 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 9151225 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 91922994 # number of integer instructions
+system.cpu1.num_func_calls 991908 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 9137643 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 91824874 # number of integer instructions
system.cpu1.num_fp_insts 48 # number of float instructions
-system.cpu1.num_int_register_reads 171998955 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 78483891 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 171791517 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 78447804 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 52229827 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 37031962 # number of times the CC registers were written
-system.cpu1.num_mem_refs 8648347 # number of memory refs
-system.cpu1.num_load_insts 5505950 # Number of load instructions
-system.cpu1.num_store_insts 3142397 # Number of store instructions
-system.cpu1.num_idle_cycles 10281439289.330288 # Number of idle cycles
-system.cpu1.num_busy_cycles 160958258.669712 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.015414 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.984586 # Percentage of idle cycles
-system.cpu1.Branches 10509152 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 118845 0.12% 0.12% # Class of executed instruction
-system.cpu1.op_class::IntAlu 89646727 91.00% 91.12% # Class of executed instruction
-system.cpu1.op_class::IntMult 68401 0.07% 91.19% # Class of executed instruction
-system.cpu1.op_class::IntDiv 39477 0.04% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 16 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::MemRead 5501755 5.58% 96.81% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3142397 3.19% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 52143431 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 36991088 # number of times the CC registers were written
+system.cpu1.num_mem_refs 8627580 # number of memory refs
+system.cpu1.num_load_insts 5530314 # Number of load instructions
+system.cpu1.num_store_insts 3097266 # Number of store instructions
+system.cpu1.num_idle_cycles 10278680276.738028 # Number of idle cycles
+system.cpu1.num_busy_cycles 160511789.261972 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.015376 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.984624 # Percentage of idle cycles
+system.cpu1.Branches 10492962 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 118368 0.12% 0.12% # Class of executed instruction
+system.cpu1.op_class::IntAlu 89576077 91.01% 91.13% # Class of executed instruction
+system.cpu1.op_class::IntMult 66940 0.07% 91.20% # Class of executed instruction
+system.cpu1.op_class::IntDiv 40064 0.04% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 16 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::MemRead 5526131 5.61% 96.85% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3097266 3.15% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 98517618 # Class of executed instruction
-system.iobus.trans_dist::ReadReq 883857 # Transaction distribution
-system.iobus.trans_dist::ReadResp 883857 # Transaction distribution
-system.iobus.trans_dist::WriteReq 36766 # Transaction distribution
-system.iobus.trans_dist::WriteResp 36766 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1833 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1833 # Transaction distribution
+system.cpu1.op_class::total 98424862 # Class of executed instruction
+system.iobus.trans_dist::ReadReq 883871 # Transaction distribution
+system.iobus.trans_dist::ReadResp 883871 # Transaction distribution
+system.iobus.trans_dist::WriteReq 36792 # Transaction distribution
+system.iobus.trans_dist::WriteResp 36792 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1835 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1835 # Transaction distribution
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6154 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6166 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1422 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1234 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14468 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811270 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 178 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1754122 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811278 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 2214 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1753576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4922 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 676 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 876 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12896 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 13284 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 70 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 87372 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1844912 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 72 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4620 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 92 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 88002 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 1844996 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3506 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2844 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2468 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7234 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622534 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 356 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2100077 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7044 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622550 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 360 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 4401 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2099537 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1352 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1752 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6642 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 140 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52465 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2159378 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 144 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9237 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 53095 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2159468 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 9039000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 9083500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 159000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 944500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 945000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 84500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy 51500 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 51500 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 21127500 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 21127500 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 458718000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 1783484 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 1770984 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 31828500 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 31828500 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy 2500 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 20524000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20526000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 410414499 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 410368779 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 7700146 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 7668139 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 1592000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2481464 # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy 1751500 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2638190 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1948163500 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1947717500 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 60411500 # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy 60917000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.ruby.clk_domain.clock 500 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 11180744 # delay histogram for all message
-system.ruby.delayHist::mean 0.431770 # delay histogram for all message
-system.ruby.delayHist::stdev 1.809571 # delay histogram for all message
-system.ruby.delayHist | 10577839 94.61% 94.61% | 2056 0.02% 94.63% | 600268 5.37% 99.99% | 190 0.00% 100.00% | 314 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 11180744 # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size 1
-system.ruby.outstanding_req_hist::max_bucket 9
-system.ruby.outstanding_req_hist::samples 197955014
-system.ruby.outstanding_req_hist::mean 1.000129
-system.ruby.outstanding_req_hist::gmean 1.000089
-system.ruby.outstanding_req_hist::stdev 0.011356
-system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929484 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 197955014
-system.ruby.latency_hist::bucket_size 128
-system.ruby.latency_hist::max_bucket 1279
-system.ruby.latency_hist::samples 197955013
-system.ruby.latency_hist::mean 1.340863
-system.ruby.latency_hist::gmean 1.042158
-system.ruby.latency_hist::stdev 5.086284
-system.ruby.latency_hist | 197919444 99.98% 99.98% | 26717 0.01% 100.00% | 2924 0.00% 100.00% | 3327 0.00% 100.00% | 1642 0.00% 100.00% | 886 0.00% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00%
-system.ruby.latency_hist::total 197955013
-system.ruby.hit_latency_hist::bucket_size 1
-system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 195243076
-system.ruby.hit_latency_hist::mean 1
-system.ruby.hit_latency_hist::gmean 1
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243076 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 195243076
-system.ruby.miss_latency_hist::bucket_size 128
-system.ruby.miss_latency_hist::max_bucket 1279
-system.ruby.miss_latency_hist::samples 2711937
-system.ruby.miss_latency_hist::mean 25.880928
-system.ruby.miss_latency_hist::gmean 20.371838
-system.ruby.miss_latency_hist::stdev 35.746268
-system.ruby.miss_latency_hist | 2676368 98.69% 98.69% | 26717 0.99% 99.67% | 2924 0.11% 99.78% | 3327 0.12% 99.90% | 1642 0.06% 99.96% | 886 0.03% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00%
-system.ruby.miss_latency_hist::total 2711937
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386658 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208703 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595361 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 114457594 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 551051 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 115008645 # Number of cache demand accesses
+system.ruby.delayHist::samples 11184165 # delay histogram for all message
+system.ruby.delayHist::mean 0.431974 # delay histogram for all message
+system.ruby.delayHist::stdev 1.810021 # delay histogram for all message
+system.ruby.delayHist | 10580766 94.60% 94.60% | 2101 0.02% 94.62% | 600708 5.37% 99.99% | 188 0.00% 100.00% | 323 0.00% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 11184165 # delay histogram for all message
+system.ruby.outstanding_req_hist_seqr::bucket_size 1
+system.ruby.outstanding_req_hist_seqr::max_bucket 9
+system.ruby.outstanding_req_hist_seqr::samples 197976054
+system.ruby.outstanding_req_hist_seqr::mean 1.000129
+system.ruby.outstanding_req_hist_seqr::gmean 1.000089
+system.ruby.outstanding_req_hist_seqr::stdev 0.011359
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197950506 99.99% 99.99% | 25548 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 197976054
+system.ruby.latency_hist_seqr::bucket_size 128
+system.ruby.latency_hist_seqr::max_bucket 1279
+system.ruby.latency_hist_seqr::samples 197976053
+system.ruby.latency_hist_seqr::mean 1.340875
+system.ruby.latency_hist_seqr::gmean 1.042170
+system.ruby.latency_hist_seqr::stdev 5.085216
+system.ruby.latency_hist_seqr | 197940485 99.98% 99.98% | 26707 0.01% 100.00% | 2933 0.00% 100.00% | 3350 0.00% 100.00% | 1606 0.00% 100.00% | 905 0.00% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 197976053
+system.ruby.hit_latency_hist_seqr::bucket_size 1
+system.ruby.hit_latency_hist_seqr::max_bucket 9
+system.ruby.hit_latency_hist_seqr::samples 195263006
+system.ruby.hit_latency_hist_seqr::mean 1
+system.ruby.hit_latency_hist_seqr::gmean 1
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195263006 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 195263006
+system.ruby.miss_latency_hist_seqr::bucket_size 128
+system.ruby.miss_latency_hist_seqr::max_bucket 1279
+system.ruby.miss_latency_hist_seqr::samples 2713047
+system.ruby.miss_latency_hist_seqr::mean 25.874270
+system.ruby.miss_latency_hist_seqr::gmean 20.370607
+system.ruby.miss_latency_hist_seqr::stdev 35.731774
+system.ruby.miss_latency_hist_seqr | 2677479 98.69% 98.69% | 26707 0.98% 99.67% | 2933 0.11% 99.78% | 3350 0.12% 99.90% | 1606 0.06% 99.96% | 905 0.03% 100.00% | 4 0.00% 100.00% | 34 0.00% 100.00% | 22 0.00% 100.00% | 7 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 2713047
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 16414226 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 1206044 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17620270 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 114568727 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 549758 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 115118485 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 7947911 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 682965 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8630876 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 56450913 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 269218 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 56720131 # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 7924165 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 686474 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8610639 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 56355888 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 270771 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 56626659 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits 2479106 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 232831 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2711937 # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits 2479845 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 233202 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 2713047 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 0.059056
-system.ruby.network.routers0.msg_count.Control::0 1759754
-system.ruby.network.routers0.msg_count.Request_Control::2 45501
-system.ruby.network.routers0.msg_count.Response_Data::1 1788735
-system.ruby.network.routers0.msg_count.Response_Control::1 1174106
-system.ruby.network.routers0.msg_count.Response_Control::2 1170476
-system.ruby.network.routers0.msg_count.Writeback_Data::0 411011
-system.ruby.network.routers0.msg_count.Writeback_Data::1 193
-system.ruby.network.routers0.msg_count.Writeback_Control::0 718896
-system.ruby.network.routers0.msg_bytes.Control::0 14078032
-system.ruby.network.routers0.msg_bytes.Request_Control::2 364008
-system.ruby.network.routers0.msg_bytes.Response_Data::1 128788920
-system.ruby.network.routers0.msg_bytes.Response_Control::1 9392848
-system.ruby.network.routers0.msg_bytes.Response_Control::2 9363808
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 29592792
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 13896
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 5751168
-system.ruby.network.routers1.percent_links_utilized 0.031129
-system.ruby.network.routers1.msg_count.Control::0 952183
-system.ruby.network.routers1.msg_count.Request_Control::2 41487
-system.ruby.network.routers1.msg_count.Response_Data::1 977973
-system.ruby.network.routers1.msg_count.Response_Control::1 652847
-system.ruby.network.routers1.msg_count.Response_Control::2 651858
-system.ruby.network.routers1.msg_count.Writeback_Data::0 161021
-system.ruby.network.routers1.msg_count.Writeback_Data::1 301
-system.ruby.network.routers1.msg_count.Writeback_Control::0 450874
-system.ruby.network.routers1.msg_bytes.Control::0 7617464
-system.ruby.network.routers1.msg_bytes.Request_Control::2 331896
-system.ruby.network.routers1.msg_bytes.Response_Data::1 70414056
-system.ruby.network.routers1.msg_bytes.Response_Control::1 5222776
-system.ruby.network.routers1.msg_bytes.Response_Control::2 5214864
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 11593512
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 21672
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 3606992
-system.ruby.network.routers2.percent_links_utilized 0.094716
-system.ruby.network.routers2.msg_count.Control::0 2893171
-system.ruby.network.routers2.msg_count.Request_Control::2 85123
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system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers4.throttle1.link_utilization 0.000228
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system.ruby.network.routers6.throttle4.link_utilization 0.000259
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system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers6.throttle5.link_utilization 0
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
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-system.ruby.delayVCHist.vnet_0::stdev 2.309515 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5702895 90.87% 90.87% | 563 0.01% 90.88% | 572045 9.11% 99.99% | 184 0.00% 99.99% | 309 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6276073 # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_0::mean 0.731657 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 2.309527 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 5704590 90.87% 90.87% | 579 0.01% 90.88% | 572160 9.11% 99.99% | 182 0.00% 99.99% | 317 0.01% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 6277907 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
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-system.ruby.delayVCHist.vnet_1::mean 0.048845 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.619508 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4787335 99.37% 99.37% | 621 0.01% 99.38% | 650 0.01% 99.40% | 843 0.02% 99.41% | 27983 0.58% 99.99% | 240 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 4817683 # delay histogram for vnet_1
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+system.ruby.delayVCHist.vnet_1 | 4787836 99.36% 99.36% | 592 0.01% 99.38% | 677 0.01% 99.39% | 845 0.02% 99.41% | 28317 0.59% 99.99% | 231 0.00% 100.00% | 4 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1
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system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 86988 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.000184 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.019179 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 86980 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 86988 # delay histogram for vnet_2
-system.ruby.LD.latency_hist::bucket_size 128
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-system.ruby.LD.latency_hist::stdev 9.014347
-system.ruby.LD.latency_hist | 15417213 99.90% 99.90% | 12849 0.08% 99.99% | 809 0.01% 99.99% | 750 0.00% 100.00% | 322 0.00% 100.00% | 89 0.00% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
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-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998284 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.LD.miss_latency_hist::stdev 22.661921
-system.ruby.LD.miss_latency_hist | 1418929 98.97% 98.97% | 12849 0.90% 99.86% | 809 0.06% 99.92% | 750 0.05% 99.97% | 322 0.02% 99.99% | 89 0.01% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
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-system.ruby.ST.latency_hist::gmean 1.143928
-system.ruby.ST.latency_hist::stdev 17.959095
-system.ruby.ST.latency_hist | 9598428 99.85% 99.85% | 8674 0.09% 99.94% | 1607 0.02% 99.96% | 2294 0.02% 99.98% | 1185 0.01% 99.99% | 751 0.01% 100.00% | 6 0.00% 100.00% | 22 0.00% 100.00% | 16 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.latency_hist::total 9612989
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-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259406 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.hit_latency_hist::total 9259406
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-system.ruby.ST.miss_latency_hist::max_bucket 1279
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-system.ruby.ST.miss_latency_hist::mean 61.823054
-system.ruby.ST.miss_latency_hist::gmean 38.699181
-system.ruby.ST.miss_latency_hist::stdev 72.148162
-system.ruby.ST.miss_latency_hist | 339022 95.88% 95.88% | 8674 2.45% 98.34% | 1607 0.45% 98.79% | 2294 0.65% 99.44% | 1185 0.34% 99.77% | 751 0.21% 99.99% | 6 0.00% 99.99% | 22 0.01% 99.99% | 16 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 353583
-system.ruby.IFETCH.latency_hist::bucket_size 128
-system.ruby.IFETCH.latency_hist::max_bucket 1279
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-system.ruby.IFETCH.latency_hist::stdev 1.876064
-system.ruby.IFETCH.latency_hist | 171723049 100.00% 100.00% | 4816 0.00% 100.00% | 477 0.00% 100.00% | 266 0.00% 100.00% | 120 0.00% 100.00% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist::total 171728776
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-system.ruby.IFETCH.hit_latency_hist::mean 1
-system.ruby.IFETCH.hit_latency_hist::gmean 1
-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908507 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist::total 170908507
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-system.ruby.IFETCH.miss_latency_hist | 814542 99.30% 99.30% | 4816 0.59% 99.89% | 477 0.06% 99.95% | 266 0.03% 99.98% | 120 0.01% 99.99% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.latency_hist::max_bucket 1279
-system.ruby.RMW_Read.latency_hist::samples 500824
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-system.ruby.RMW_Read.latency_hist::stdev 10.245462
-system.ruby.RMW_Read.latency_hist | 500634 99.96% 99.96% | 144 0.03% 99.99% | 19 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.RMW_Read.hit_latency_hist::mean 1
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-system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 434823 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.hit_latency_hist::total 434823
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-system.ruby.RMW_Read.miss_latency_hist::stdev 18.490127
-system.ruby.RMW_Read.miss_latency_hist | 65811 99.71% 99.71% | 144 0.22% 99.93% | 19 0.03% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.RMW_Read.miss_latency_hist::total 66001
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639
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-system.ruby.Locked_RMW_Read.latency_hist::stdev 8.375867
-system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 4 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total 340189
-system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867
-system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1
-system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total 301867
-system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64
-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38322
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean 21.616591
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 20.468877
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.672180
-system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 90 0.23% 99.33% | 233 0.61% 99.93% | 1 0.00% 99.94% | 4 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total 38322
-system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.latency_hist::samples 340189
-system.ruby.Locked_RMW_Write.latency_hist::mean 1
-system.ruby.Locked_RMW_Write.latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total 340189
-system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1
-system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9
-system.ruby.Locked_RMW_Write.hit_latency_hist::samples 340189
-system.ruby.Locked_RMW_Write.hit_latency_hist::mean 1
-system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 1
-system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist::total 340189
-system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00%
-system.ruby.Directory_Controller.Data 103288 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 147284 0.00% 0.00%
-system.ruby.Directory_Controller.DMA_READ 819 0.00% 0.00%
+system.ruby.delayVCHist.vnet_2::samples 87748 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.000137 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 0.016538 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 87742 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 87748 # delay histogram for vnet_2
+system.ruby.LD.latency_hist_seqr::bucket_size 128
+system.ruby.LD.latency_hist_seqr::max_bucket 1279
+system.ruby.LD.latency_hist_seqr::samples 15434919
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+system.ruby.LD.latency_hist_seqr::stdev 9.010453
+system.ruby.LD.latency_hist_seqr | 15420072 99.90% 99.90% | 12855 0.08% 99.99% | 824 0.01% 99.99% | 752 0.00% 100.00% | 311 0.00% 100.00% | 93 0.00% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
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+system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
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+system.ruby.LD.hit_latency_hist_seqr::mean 1
+system.ruby.LD.hit_latency_hist_seqr::gmean 1
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+system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
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+system.ruby.LD.miss_latency_hist_seqr::gmean 18.789020
+system.ruby.LD.miss_latency_hist_seqr::stdev 22.643422
+system.ruby.LD.miss_latency_hist_seqr | 1419275 98.96% 98.96% | 12855 0.90% 99.86% | 824 0.06% 99.92% | 752 0.05% 99.97% | 311 0.02% 99.99% | 93 0.01% 100.00% | 1 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 1434122
+system.ruby.ST.latency_hist_seqr::bucket_size 128
+system.ruby.ST.latency_hist_seqr::max_bucket 1279
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+system.ruby.ST.latency_hist_seqr::gmean 1.144007
+system.ruby.ST.latency_hist_seqr::stdev 17.965589
+system.ruby.ST.latency_hist_seqr | 9599857 99.85% 99.85% | 8650 0.09% 99.94% | 1610 0.02% 99.96% | 2319 0.02% 99.98% | 1166 0.01% 99.99% | 762 0.01% 100.00% | 3 0.00% 100.00% | 22 0.00% 100.00% | 17 0.00% 100.00% | 5 0.00% 100.00%
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+system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
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+system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
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+system.ruby.ST.miss_latency_hist_seqr::gmean 38.656662
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+system.ruby.ST.miss_latency_hist_seqr | 339370 95.89% 95.89% | 8650 2.44% 98.33% | 1610 0.45% 98.79% | 2319 0.66% 99.44% | 1166 0.33% 99.77% | 762 0.22% 99.99% | 3 0.00% 99.99% | 22 0.01% 99.99% | 17 0.00% 100.00% | 5 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::total 353924
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 128
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+system.ruby.IFETCH.latency_hist_seqr | 171739420 100.00% 100.00% | 4825 0.00% 100.00% | 474 0.00% 100.00% | 262 0.00% 100.00% | 112 0.00% 100.00% | 43 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
+system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
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+system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
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+system.ruby.IFETCH.hit_latency_hist_seqr::total 170924615
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
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+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 19.917428
+system.ruby.IFETCH.miss_latency_hist_seqr | 814805 99.30% 99.30% | 4825 0.59% 99.89% | 474 0.06% 99.95% | 262 0.03% 99.98% | 112 0.01% 99.99% | 43 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::total 820529
+system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128
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+system.ruby.RMW_Read.latency_hist_seqr::stdev 10.213309
+system.ruby.RMW_Read.latency_hist_seqr | 500762 99.96% 99.96% | 143 0.03% 99.99% | 15 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1
+system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9
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+system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1
+system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434941 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.hit_latency_hist_seqr::total 434941
+system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128
+system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279
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+system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.367061
+system.ruby.RMW_Read.miss_latency_hist_seqr | 65821 99.72% 99.72% | 143 0.22% 99.94% | 15 0.02% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.RMW_Read.miss_latency_hist_seqr::total 66006
+system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64
+system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639
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+system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.468226
+system.ruby.Locked_RMW_Read.latency_hist_seqr | 339968 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 7 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 6 0.00% 100.00%
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+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1
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+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301850
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1
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+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38466
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+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.474141
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 16.027002
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 38118 99.10% 99.10% | 90 0.23% 99.33% | 233 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 7 0.02% 99.96% | 5 0.01% 99.98% | 1 0.00% 99.98% | 2 0.01% 99.98% | 6 0.02% 100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38466
+system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9
+system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340316
+system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1
+system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340316
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340316
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340316 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340316
+system.ruby.Directory_Controller.Fetch 181113 0.00% 0.00%
+system.ruby.Directory_Controller.Data 102911 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 181583 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 147234 0.00% 0.00%
+system.ruby.Directory_Controller.DMA_READ 816 0.00% 0.00%
system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 13460 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 181234 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_READ 474 0.00% 0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE 43996 0.00% 0.00%
-system.ruby.Directory_Controller.ID.Memory_Data 474 0.00% 0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack 43996 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 100203 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE 2740 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 13460 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 181234 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 100203 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWR.Data 2740 0.00% 0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2740 0.00% 0.00%
-system.ruby.DMA_Controller.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.ReadRequest::total 819
+system.ruby.Directory_Controller.CleanReplacement 13434 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 181113 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE 44323 0.00% 0.00%
+system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack 44323 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 100152 0.00% 0.00%
+system.ruby.Directory_Controller.M.DMA_READ 346 0.00% 0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE 2413 0.00% 0.00%
+system.ruby.Directory_Controller.M.CleanReplacement 13434 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 181113 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 100152 0.00% 0.00%
+system.ruby.Directory_Controller.M_DRD.Data 346 0.00% 0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack 346 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWR.Data 2413 0.00% 0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2413 0.00% 0.00%
+system.ruby.DMA_Controller.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.ReadRequest::total 816
system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.WriteRequest::total 46736
-system.ruby.DMA_Controller.Data | 819 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.Data::total 819
+system.ruby.DMA_Controller.Data | 816 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Data::total 816
system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.Ack::total 46736
-system.ruby.DMA_Controller.READY.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total 819
+system.ruby.DMA_Controller.READY.ReadRequest | 816 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.ReadRequest::total 816
system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.READY.WriteRequest::total 46736
-system.ruby.DMA_Controller.BUSY_RD.Data | 819 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total 819
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system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736
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-system.ruby.L1Cache_Controller.Fwd_GETX::total 24111
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system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.Data | 528 32.39% 32.39% | 1102 67.61% 100.00%
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-system.ruby.L1Cache_Controller.Ack | 12681 52.16% 52.16% | 11631 47.84% 100.00%
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-system.ruby.L1Cache_Controller.NP.Store | 298756 70.81% 70.81% | 123170 29.19% 100.00%
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system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4
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system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00%
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-system.ruby.L2Cache_Controller.M.L1_GETX 274075 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 99609 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6704 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 2851 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1304540 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 274254 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 99553 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6682 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv 2525 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 27482 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 24111 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1741802 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 251 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 27819 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 24266 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 1741763 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 256 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 133 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 116748 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 2851 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 442 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 116345 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv 2525 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 447 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 52 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1570 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 6674 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 296 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 53 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 80 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 1551 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 6672 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 294 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 295 0.00% 0.00%
system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 32321 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 15428 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 133485 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 235 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 32337 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 15422 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 133354 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS 237 0.00% 0.00%
system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26235 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 157 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26522 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 165 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768613 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25310 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2170 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768751 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25603 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2212 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 27480 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 27815 0.00% 0.00%
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff