stats: x86: update stats missed out on in preivous changeset

[gem5.git] / tests / long / fs / 10.linux-boot / ref / x86 / linux / pc-switcheroo-full / config.ini

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 42cb40700af75c55683c7a981dc49d570165b1d6..57635b8c2efb40d1c8cee93b53d07934359bbf12 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
+children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
 cache_line_size=64
@@ -20,13 +20,16 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
+kernel_addr_check=true
 load_addr_mask=18446744073709551615
+load_offset=0
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
-readfile=tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -73,7 +76,7 @@ type=Bridge
 clk_domain=system.clk_domain
 delay=50000
 eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -82,12 +85,15 @@ slave=system.membus.master[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=AtomicSimpleCPU
 children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
+branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
@@ -109,12 +115,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
 simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
+socket_id=0
 switched_out=false
 system=system
 tracer=system.cpu0.tracer
@@ -135,10 +139,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -149,7 +154,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -185,10 +189,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -199,7 +204,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -252,6 +256,7 @@ eventq_index=0
 [system.cpu1]
 type=TimingSimpleCPU
 children=dtb isa itb tracer
+branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
@@ -273,6 +278,7 @@ numThreads=1
 profile=0
 progress_interval=0
 simpoint_start_insts=
+socket_id=0
 switched_out=true
 system=system
 tracer=system.cpu1.tracer
@@ -345,6 +351,7 @@ do_statistics_insts=true
 dtb=system.cpu2.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -390,18 +397,18 @@ smtLSQThreshold=100
 smtNumFetchingThreads=1
 smtROBPolicy=Partitioned
 smtROBThreshold=100
+socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=true
 system=system
 tracer=system.cpu2.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=
 
 [system.cpu2.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -415,7 +422,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu2.dtb]
 type=X86TLB
@@ -447,9 +453,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -461,16 +467,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
-opLat=20
+opLat=1
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -482,23 +488,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -510,23 +516,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -538,9 +544,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -552,142 +558,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -699,9 +705,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -713,16 +719,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -734,9 +740,9 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.isa]
 type=X86ISA
@@ -763,13 +769,23 @@ eventq_index=0
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.e820_table]
 type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
 eventq_index=0
 
 [system.e820_table.entries0]
@@ -795,6 +811,13 @@ size=133169152
 
 [system.e820_table.entries3]
 type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
 addr=4294901760
 eventq_index=0
 range_type=2
@@ -843,13 +866,13 @@ version=17
 [system.intel_mp_table.base_entries02]
 type=X86IntelMPBus
 bus_id=0
-bus_type=ISA
+bus_type=PCI
 eventq_index=0
 
 [system.intel_mp_table.base_entries03]
 type=X86IntelMPBus
 bus_id=1
-bus_type=PCI
+bus_type=ISA
 eventq_index=0
 
 [system.intel_mp_table.base_entries04]
@@ -859,7 +882,7 @@ dest_io_apic_intin=16
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
 source_bus_irq=16
 trigger=ConformTrigger
 
@@ -870,7 +893,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=0
 trigger=ConformTrigger
 
@@ -881,7 +904,7 @@ dest_io_apic_intin=2
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=0
 trigger=ConformTrigger
 
@@ -892,7 +915,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=1
 trigger=ConformTrigger
 
@@ -903,7 +926,7 @@ dest_io_apic_intin=1
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=1
 trigger=ConformTrigger
 
@@ -914,7 +937,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=3
 trigger=ConformTrigger
 
@@ -925,7 +948,7 @@ dest_io_apic_intin=3
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=3
 trigger=ConformTrigger
 
@@ -936,7 +959,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=4
 trigger=ConformTrigger
 
@@ -947,7 +970,7 @@ dest_io_apic_intin=4
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=4
 trigger=ConformTrigger
 
@@ -958,7 +981,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=5
 trigger=ConformTrigger
 
@@ -969,7 +992,7 @@ dest_io_apic_intin=5
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=5
 trigger=ConformTrigger
 
@@ -980,7 +1003,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=6
 trigger=ConformTrigger
 
@@ -991,7 +1014,7 @@ dest_io_apic_intin=6
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=6
 trigger=ConformTrigger
 
@@ -1002,7 +1025,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=7
 trigger=ConformTrigger
 
@@ -1013,7 +1036,7 @@ dest_io_apic_intin=7
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=7
 trigger=ConformTrigger
 
@@ -1024,7 +1047,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=8
 trigger=ConformTrigger
 
@@ -1035,7 +1058,7 @@ dest_io_apic_intin=8
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=8
 trigger=ConformTrigger
 
@@ -1046,7 +1069,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=9
 trigger=ConformTrigger
 
@@ -1057,7 +1080,7 @@ dest_io_apic_intin=9
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=9
 trigger=ConformTrigger
 
@@ -1068,7 +1091,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=10
 trigger=ConformTrigger
 
@@ -1079,7 +1102,7 @@ dest_io_apic_intin=10
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=10
 trigger=ConformTrigger
 
@@ -1090,7 +1113,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=11
 trigger=ConformTrigger
 
@@ -1101,7 +1124,7 @@ dest_io_apic_intin=11
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=11
 trigger=ConformTrigger
 
@@ -1112,7 +1135,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=12
 trigger=ConformTrigger
 
@@ -1123,7 +1146,7 @@ dest_io_apic_intin=12
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=12
 trigger=ConformTrigger
 
@@ -1134,7 +1157,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=13
 trigger=ConformTrigger
 
@@ -1145,7 +1168,7 @@ dest_io_apic_intin=13
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=13
 trigger=ConformTrigger
 
@@ -1156,7 +1179,7 @@ dest_io_apic_intin=0
 eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=14
 trigger=ConformTrigger
 
@@ -1167,15 +1190,15 @@ dest_io_apic_intin=14
 eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
 source_bus_irq=14
 trigger=ConformTrigger
 
 [system.intel_mp_table.ext_entries]
 type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
 eventq_index=0
-parent_bus=1
+parent_bus=0
 subtractive_decode=true
 
 [system.intrctrl]
@@ -1184,14 +1207,16 @@ eventq_index=0
 sys=system
 
 [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
-use_default_range=true
-width=8
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=false
+width=16
 default=system.pc.pciconfig.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
@@ -1200,10 +1225,11 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1214,9 +1240,8 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[18]
+cpu_side=system.iobus.master[19]
 mem_side=system.membus.slave[4]
 
 [system.iocache.tags]
@@ -1235,10 +1260,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1249,7 +1275,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
@@ -1265,14 +1290,18 @@ sequential_access=false
 size=4194304
 
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
@@ -1297,7 +1326,7 @@ pio=system.membus.default
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1318,7 +1347,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[12]
+pio=system.iobus.master[13]
 
 [system.pc.com_1]
 type=Uart8250
@@ -1330,7 +1359,7 @@ pio_latency=100000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
+pio=system.iobus.master[14]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -1356,7 +1385,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[14]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -1374,7 +1403,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[16]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1392,7 +1421,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[17]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1410,9 +1439,9 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[17]
+pio=system.iobus.master[18]
 
-[system.pc.i_dont_exist]
+[system.pc.i_dont_exist1]
 type=IsaFake
 clk_domain=system.clk_domain
 eventq_index=0
@@ -1430,6 +1459,24 @@ update_data=false
 warn_access=
 pio=system.iobus.master[11]
 
+[system.pc.i_dont_exist2]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=9223372036854776045
+pio_latency=100000
+pio_size=1
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
 [system.pc.pciconfig]
 type=PciConfigAll
 bus=0
@@ -1514,6 +1561,7 @@ HeaderType=0
 InterruptLine=14
 InterruptPin=1
 LatencyTimer=0
+LegacyIOBase=9223372036854775808
 MSICAPBaseOffset=0
 MSICAPCapId=0
 MSICAPMaskBits=0
@@ -1591,7 +1639,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-x86.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1614,7 +1662,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1803,9 +1851,34 @@ system=system
 pio=system.iobus.master[9]
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -1813,30 +1886,45 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
+tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[3]
 
 [system.smbios_table]
@@ -1863,13 +1951,17 @@ vendor=
 version=
 
 [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
-width=8
+width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port