sim_ticks 1800193398000 # Number of ticks simulated
final_tick 1800193398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 392596 # Simulator instruction rate (inst/s)
-host_op_rate 723379 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 803099848 # Simulator tick rate (ticks/s)
-host_mem_usage 292568 # Number of bytes of host memory used
-host_seconds 2241.56 # Real time elapsed on the host
+host_inst_rate 510604 # Simulator instruction rate (inst/s)
+host_op_rate 940816 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1044499940 # Simulator tick rate (ticks/s)
+host_mem_usage 295340 # Number of bytes of host memory used
+host_seconds 1723.50 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493928 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1049487 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5039 # Transaction distribution
+system.membus.trans_dist::ReadResp 5039 # Transaction distribution
+system.membus.trans_dist::Writeback 2511 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21970 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21970 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1889280 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3600386796 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.committedOps 1621493928 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354440 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_func_calls 2123381 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354440 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff