---------- Begin Simulation Statistics ----------
-sim_seconds 0.026877 # Number of seconds simulated
-sim_ticks 26877484000 # Number of ticks simulated
-final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175198 # Simulator instruction rate (inst/s)
-host_op_rate 176456 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51980195 # Simulator tick rate (ticks/s)
-host_mem_usage 379404 # Number of bytes of host memory used
-host_seconds 517.07 # Real time elapsed on the host
-sim_insts 90589798 # Number of instructions simulated
-sim_ops 91240351 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992384 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44928 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 702 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15506 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1671585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35250919 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 36922504 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1671585 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1671585 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15506 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 992384 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 955 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 934 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26877282500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15506 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 11153 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4230 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 3465.405018 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 823.463699 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 3831.282142 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 22 7.89% 32.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 15 5.38% 37.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 12 4.30% 41.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 10 3.58% 45.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 6 2.15% 47.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 2 0.72% 48.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 2 0.72% 49.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265 1 0.36% 59.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation
-system.physmem.totQLat 38456500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 288012750 # Sum of mem lat for all requests
-system.physmem.totBusLat 77530000 # Total cycles spent in databus access
-system.physmem.totBankLat 172026250 # Total cycles spent in bank access
-system.physmem.avgQLat 2480.10 # Average queueing delay per request
-system.physmem.avgBankLat 11094.17 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18574.28 # Average memory access latency
-system.physmem.avgRdBW 36.92 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 36.92 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.29 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 15227 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1733347.25 # Average gap between requests
-system.membus.throughput 36922504 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 968 # Transaction distribution
-system.membus.trans_dist::ReadResp 968 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 992384 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 145109998 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.cpu.branchPred.lookups 26677800 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21997882 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 841974 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11370900 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11281126 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.210493 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 69875 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 190 # Number of incorrect RAS predictions.
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53754969 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14167360 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127859416 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26677800 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11351001 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24030535 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4760658 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11306613 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13839893 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329843 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53406892 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.410540 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.214942 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29414657 55.08% 55.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3389704 6.35% 61.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2028213 3.80% 65.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1552667 2.91% 68.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1667858 3.12% 71.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2917621 5.46% 76.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1511775 2.83% 79.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1090045 2.04% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9834352 18.41% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53406892 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.496285 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.378560 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16930336 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9153085 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22398033 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1031812 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3893626 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4442083 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8660 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126043342 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42618 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3893626 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18711323 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3589161 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 177598 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21546569 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5488615 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123125799 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 427703 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4597767 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4613 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12549588 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29468785 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5519570 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2135216 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1252898 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118144684 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8486 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105149299 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 79112 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26716988 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65524839 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 268 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53406892 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.968834 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.909318 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15356551 28.75% 28.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11649216 21.81% 50.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8254544 15.46% 66.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6822524 12.77% 78.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4944372 9.26% 88.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2950581 5.52% 93.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2452903 4.59% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 533996 1.00% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 442205 0.83% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53406892 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 45764 6.91% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 341696 51.58% 58.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 274978 41.51% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74418524 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 156 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 210 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25604703 24.35% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5114728 4.86% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105149299 # Type of FU issued
-system.cpu.iq.rate 1.956085 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 662465 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264446249 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144874513 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102679810 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 818 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1193 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 350 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105811363 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 401 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 442313 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6894819 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6564 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6306 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 774726 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31505 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3893626 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 957081 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 126869 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118165864 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309166 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29468785 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5519570 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4598 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 65994 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6719 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6306 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446848 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 444951 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891799 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104175749 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25286286 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 973550 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12694 # number of nop insts executed
-system.cpu.iew.exec_refs 30344072 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21323909 # Number of branches executed
-system.cpu.iew.exec_stores 5057786 # Number of stores executed
-system.cpu.iew.exec_rate 1.937974 # Inst execution rate
-system.cpu.iew.wb_sent 102957516 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102680160 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62240823 # num instructions producing a value
-system.cpu.iew.wb_consumers 104288348 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.910152 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596815 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26915742 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833391 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49513266 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.843000 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.540951 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20021121 40.44% 40.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13151741 26.56% 67.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4165163 8.41% 75.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3429722 6.93% 82.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1536672 3.10% 85.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 726445 1.47% 86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 951437 1.92% 88.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 253528 0.51% 89.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5277437 10.66% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49513266 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90602407 # Number of instructions committed
-system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27318810 # Number of memory references committed
-system.cpu.commit.loads 22573966 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18732304 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5277437 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162398797 # The number of ROB reads
-system.cpu.rob.rob_writes 240250691 # The number of ROB writes
-system.cpu.timesIdled 46136 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 348077 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90589798 # Number of Instructions Simulated
-system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
-system.cpu.cpi 0.593389 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.593389 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.685236 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.685236 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495533268 # number of integer regfile reads
-system.cpu.int_regfile_writes 120542090 # number of integer regfile writes
-system.cpu.fp_regfile_reads 173 # number of floating regfile reads
-system.cpu.fp_regfile_writes 448 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29087390 # number of misc regfile reads
-system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4503454862 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 904620 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 904619 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 942919 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1225499 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13838909 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13838909 # number of overall hits
-system.cpu.icache.overall_hits::total 13838909 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
-system.cpu.icache.overall_misses::total 983 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 64555998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 64555998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 64555998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 64555998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 64555998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 64555998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13839892 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13839892 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13839892 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13839892 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13839892 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13839892 # number of overall (read+write) accesses
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-system.cpu.dcache.overall_miss_latency::total 21806297834 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24770918 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24770918 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11831.519388 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11831.519388 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 39186.258413 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31406.250000 # average LoadLockedReq miss latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 154131 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff