---------- Begin Simulation Statistics ----------
-sim_seconds 0.026913 # Number of seconds simulated
-sim_ticks 26912680500 # Number of ticks simulated
-final_tick 26912680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 145850 # Simulator instruction rate (inst/s)
-host_op_rate 146897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43329539 # Simulator tick rate (ticks/s)
-host_mem_usage 407732 # Number of bytes of host memory used
-host_seconds 621.12 # Real time elapsed on the host
-sim_insts 90589798 # Number of instructions simulated
-sim_ops 91240351 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1681289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35211951 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 36893241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1681289 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1681289 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1681289 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35211951 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 36893241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15514 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 988 # Per bank write bursts
-system.physmem.perBankRdBursts::1 886 # Per bank write bursts
-system.physmem.perBankRdBursts::2 943 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1049 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 956 # Per bank write bursts
-system.physmem.perBankRdBursts::10 938 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 904 # Per bank write bursts
-system.physmem.perBankRdBursts::13 865 # Per bank write bursts
-system.physmem.perBankRdBursts::14 877 # Per bank write bursts
-system.physmem.perBankRdBursts::15 896 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26912480500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 15514 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 11168 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 617 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 1603.423015 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 482.832317 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 2202.245443 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 156 25.28% 25.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 69 11.18% 36.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 40 6.48% 42.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 21 3.40% 46.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 12 1.94% 48.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 6 0.97% 49.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 26 4.21% 53.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 13 2.11% 55.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 5 0.81% 56.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 9 1.46% 57.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705 4 0.65% 58.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 4 0.65% 59.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 5 0.81% 59.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897 8 1.30% 61.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 3 0.49% 61.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 3 0.49% 62.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 3 0.49% 64.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537 19 3.08% 69.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793 3 0.49% 71.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857 3 0.49% 72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497 3 0.49% 75.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009 3 0.49% 78.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393 3 0.49% 80.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649 3 0.49% 81.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713 3 0.49% 82.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969 1 0.16% 82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097 3 0.49% 83.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161 2 0.32% 83.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417 3 0.49% 84.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673 3 0.49% 86.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121 5 0.81% 88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185 3 0.49% 89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441 7 1.13% 91.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505 2 0.32% 91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017 3 0.49% 93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337 3 0.49% 94.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657 3 0.49% 95.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681 2 0.32% 97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 617 # Bytes accessed per row activation
-system.physmem.totQLat 103133500 # Total ticks spent queuing
-system.physmem.totMemAccLat 356414750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 175711250 # Total ticks spent accessing banks
-system.physmem.avgQLat 6647.77 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 11325.98 # Average bank access latency per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 22973.75 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.29 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14897 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 96.02 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1734722.22 # Average gap between requests
-system.physmem.pageHitRate 96.02 # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent 0.95 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 36893241 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 976 # Transaction distribution
-system.membus.trans_dist::ReadResp 976 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31028 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31028 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 992896 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 19247000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 145153250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.cpu.branchPred.lookups 26684421 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22003515 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 842640 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11361703 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11279248 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.274273 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 70578 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 175 # Number of incorrect RAS predictions.
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53825362 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14170521 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127888749 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26684421 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11349826 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24033756 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4765472 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11324127 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13841798 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 328713 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53434811 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.409872 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.214791 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29439353 55.09% 55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3386965 6.34% 61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2028576 3.80% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1554110 2.91% 68.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1668608 3.12% 71.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2917595 5.46% 76.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1511603 2.83% 79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1091436 2.04% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9836565 18.41% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53434811 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.495759 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.375994 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16934142 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9169646 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22402191 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1031199 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3897633 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4442994 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8719 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126071688 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42592 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3897633 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18714767 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3594336 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 187938 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21550636 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5489501 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123153089 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 427273 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4600360 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1278 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143605134 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536434214 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 500014017 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 784 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36190948 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4612 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4610 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12546346 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29477793 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5522687 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2151443 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1269536 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118168344 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8478 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105154526 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78994 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26741749 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65618769 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 260 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53434811 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.967903 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.908534 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15376938 28.78% 28.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11654897 21.81% 50.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8243564 15.43% 66.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6824643 12.77% 78.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4966766 9.30% 88.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2946722 5.51% 93.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2453138 4.59% 98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 526074 0.98% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 442069 0.83% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53434811 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 45800 6.91% 6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340417 51.39% 58.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 276226 41.70% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74421271 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25608548 24.35% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5113387 4.86% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105154526 # Type of FU issued
-system.cpu.iq.rate 1.953624 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 662470 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006300 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264484578 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144923147 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102682900 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 749 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1045 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 323 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105816623 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 441366 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6903827 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6492 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6312 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 777843 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31495 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3897633 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 959563 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 126871 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118189516 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 310121 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29477793 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5522687 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4590 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 65719 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6709 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6312 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446751 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 446217 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 892968 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104180481 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25289750 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 974045 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12694 # number of nop insts executed
-system.cpu.iew.exec_refs 30346354 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21325110 # Number of branches executed
-system.cpu.iew.exec_stores 5056604 # Number of stores executed
-system.cpu.iew.exec_rate 1.935528 # Inst execution rate
-system.cpu.iew.wb_sent 102961531 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102683223 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62241416 # num instructions producing a value
-system.cpu.iew.wb_consumers 104299638 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.907711 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596756 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26939491 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 834010 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49537178 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.842111 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.540648 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20048697 40.47% 40.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13146284 26.54% 67.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4166513 8.41% 75.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3429547 6.92% 82.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1533299 3.10% 85.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 729419 1.47% 86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 954733 1.93% 88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 253168 0.51% 89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5275518 10.65% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49537178 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90602407 # Number of instructions committed
-system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27318810 # Number of memory references committed
-system.cpu.commit.loads 22573966 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18732304 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5275518 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162448377 # The number of ROB reads
-system.cpu.rob.rob_writes 240302265 # The number of ROB writes
-system.cpu.timesIdled 46020 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 390551 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90589798 # Number of Instructions Simulated
-system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
-system.cpu.cpi 0.594166 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.594166 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.683032 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.683032 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495553334 # number of integer regfile reads
-system.cpu.int_regfile_writes 120547287 # number of integer regfile writes
-system.cpu.fp_regfile_reads 170 # number of floating regfile reads
-system.cpu.fp_regfile_writes 410 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29088502 # number of misc regfile reads
-system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4497529557 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 904650 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 904650 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 43698 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 43698 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838143 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2839608 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46848 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 1888541000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1424134990 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 3 # number of replacements
-system.cpu.icache.tags.tagsinuse 633.195127 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13840808 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 732 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18908.207650 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 633.195127 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.309177 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.309177 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13840808 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13840808 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13840808 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13840808 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13840808 # number of overall hits
-system.cpu.icache.overall_hits::total 13840808 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 989 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 989 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 989 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 989 # number of overall misses
-system.cpu.icache.overall_misses::total 989 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 66791248 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 66791248 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 66791248 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 66791248 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 66791248 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 66791248 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13841797 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13841797 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13841797 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13841797 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13841797 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13841797 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67534.123357 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67534.123357 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67534.123357 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67534.123357 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67534.123357 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 54.181818 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 256 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 256 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 256 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 256 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50590750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 50590750 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50590750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 50590750 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50590750 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 50590750 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69018.758527 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69018.758527 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69018.758527 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69018.758527 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10730.387703 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1831429 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 118.179583 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 9881.039169 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 619.212620 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 230.135914 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.301545 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018897 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.007023 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.327465 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 903638 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 903662 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 29160 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 29160 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 932798 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 932822 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 932798 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932822 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 708 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 987 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 708 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15525 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 708 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15525 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49612500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21119250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 70731750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962947000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 962947000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 49612500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 984066250 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1033678750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 49612500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 984066250 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 1033678750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 732 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 903917 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 904649 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 43698 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 43698 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 732 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947615 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948347 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 732 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947615 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948347 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967213 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332693 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.332693 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967213 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016371 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967213 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016371 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70074.152542 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75696.236559 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71663.373860 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66236.552483 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66236.552483 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66581.561997 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70074.152542 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66414.675710 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66581.561997 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 707 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 976 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40706750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17150500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57857250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780571000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780571000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40706750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797721500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 838428250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40706750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797721500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 838428250 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001079 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332693 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332693 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965847 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015626 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57576.732673 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63756.505576 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59279.969262 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53691.773284 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53691.773284 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57576.732673 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53874.620112 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54043.331829 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 943519 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3671.753264 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 28141899 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 947615 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.697608 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 8006034000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3671.753264 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.896424 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.896424 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23601231 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23601231 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4532867 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4532867 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28134098 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28134098 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28134098 # number of overall hits
-system.cpu.dcache.overall_hits::total 28134098 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1173780 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1173780 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 202114 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 202114 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1375894 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1375894 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1375894 # number of overall misses
-system.cpu.dcache.overall_misses::total 1375894 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893621478 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 13893621478 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8458573839 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8458573839 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 22352195317 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 22352195317 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 22352195317 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 22352195317 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24775011 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24775011 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3917 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3917 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29509992 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29509992 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29509992 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29509992 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047378 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.047378 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042685 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.042685 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11836.648672 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11836.648672 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41850.509312 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41850.509312 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16245.579468 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.579468 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16245.579468 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 154256 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.440483 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks
-system.cpu.dcache.writebacks::total 942911 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269842 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 269842 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158436 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 158436 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 428278 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 428278 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 428278 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 428278 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903938 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 903938 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43678 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43678 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947616 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947616 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947616 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947616 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994572760 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994572760 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319332173 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319332173 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313904933 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11313904933 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313904933 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11313904933 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036486 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036486 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032112 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032112 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032112 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.701632 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.701632 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30205.874193 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30205.874193 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.335061 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.335061 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+sim_seconds 0.058521
+sim_ticks 58521086000
+final_tick 58521086000
+sim_freq 1000000000000
+host_inst_rate 103970
+host_op_rate 104488
+host_tick_rate 67164623
+host_mem_usage 503044
+host_seconds 871.31
+sim_insts 90589799
+sim_ops 91041030
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.physmem.bytes_read::cpu.inst 44736
+system.physmem.bytes_read::cpu.data 220224
+system.physmem.bytes_read::cpu.l2cache.prefetcher 921920
+system.physmem.bytes_read::total 1186880
+system.physmem.bytes_inst_read::cpu.inst 44736
+system.physmem.bytes_inst_read::total 44736
+system.physmem.bytes_written::writebacks 4736
+system.physmem.bytes_written::total 4736
+system.physmem.num_reads::cpu.inst 699
+system.physmem.num_reads::cpu.data 3441
+system.physmem.num_reads::cpu.l2cache.prefetcher 14405
+system.physmem.num_reads::total 18545
+system.physmem.num_writes::writebacks 74
+system.physmem.num_writes::total 74
+system.physmem.bw_read::cpu.inst 764442
+system.physmem.bw_read::cpu.data 3763156
+system.physmem.bw_read::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_read::total 20281237
+system.physmem.bw_inst_read::cpu.inst 764442
+system.physmem.bw_inst_read::total 764442
+system.physmem.bw_write::writebacks 80928
+system.physmem.bw_write::total 80928
+system.physmem.bw_total::writebacks 80928
+system.physmem.bw_total::cpu.inst 764442
+system.physmem.bw_total::cpu.data 3763156
+system.physmem.bw_total::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_total::total 20362165
+system.physmem.readReqs 18546
+system.physmem.writeReqs 74
+system.physmem.readBursts 18546
+system.physmem.writeBursts 74
+system.physmem.bytesReadDRAM 1183360
+system.physmem.bytesReadWrQ 3584
+system.physmem.bytesWritten 3328
+system.physmem.bytesReadSys 1186944
+system.physmem.bytesWrittenSys 4736
+system.physmem.servicedByWrQ 56
+system.physmem.mergedWrBursts 4
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 3297
+system.physmem.perBankRdBursts::1 920
+system.physmem.perBankRdBursts::2 949
+system.physmem.perBankRdBursts::3 1031
+system.physmem.perBankRdBursts::4 1067
+system.physmem.perBankRdBursts::5 1119
+system.physmem.perBankRdBursts::6 1093
+system.physmem.perBankRdBursts::7 1097
+system.physmem.perBankRdBursts::8 1024
+system.physmem.perBankRdBursts::9 961
+system.physmem.perBankRdBursts::10 934
+system.physmem.perBankRdBursts::11 899
+system.physmem.perBankRdBursts::12 902
+system.physmem.perBankRdBursts::13 895
+system.physmem.perBankRdBursts::14 1399
+system.physmem.perBankRdBursts::15 903
+system.physmem.perBankWrBursts::0 1
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 2
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 1
+system.physmem.perBankWrBursts::5 14
+system.physmem.perBankWrBursts::6 9
+system.physmem.perBankWrBursts::7 3
+system.physmem.perBankWrBursts::8 1
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 2
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 1
+system.physmem.perBankWrBursts::13 12
+system.physmem.perBankWrBursts::14 5
+system.physmem.perBankWrBursts::15 1
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 58521077500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 18546
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 74
+system.physmem.rdQLenPdf::0 12593
+system.physmem.rdQLenPdf::1 3390
+system.physmem.rdQLenPdf::2 500
+system.physmem.rdQLenPdf::3 409
+system.physmem.rdQLenPdf::4 319
+system.physmem.rdQLenPdf::5 301
+system.physmem.rdQLenPdf::6 297
+system.physmem.rdQLenPdf::7 299
+system.physmem.rdQLenPdf::8 279
+system.physmem.rdQLenPdf::9 103
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 3
+system.physmem.wrQLenPdf::16 3
+system.physmem.wrQLenPdf::17 4
+system.physmem.wrQLenPdf::18 3
+system.physmem.wrQLenPdf::19 3
+system.physmem.wrQLenPdf::20 3
+system.physmem.wrQLenPdf::21 3
+system.physmem.wrQLenPdf::22 3
+system.physmem.wrQLenPdf::23 3
+system.physmem.wrQLenPdf::24 3
+system.physmem.wrQLenPdf::25 3
+system.physmem.wrQLenPdf::26 3
+system.physmem.wrQLenPdf::27 3
+system.physmem.wrQLenPdf::28 3
+system.physmem.wrQLenPdf::29 3
+system.physmem.wrQLenPdf::30 3
+system.physmem.wrQLenPdf::31 3
+system.physmem.wrQLenPdf::32 3
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 3004
+system.physmem.bytesPerActivate::mean 394.652463
+system.physmem.bytesPerActivate::gmean 214.589229
+system.physmem.bytesPerActivate::stdev 405.543781
+system.physmem.bytesPerActivate::0-127 893 29.73% 29.73%
+system.physmem.bytesPerActivate::128-255 965 32.12% 61.85%
+system.physmem.bytesPerActivate::256-383 89 2.96% 64.81%
+system.physmem.bytesPerActivate::384-511 63 2.10% 66.91%
+system.physmem.bytesPerActivate::512-639 67 2.23% 69.14%
+system.physmem.bytesPerActivate::640-767 66 2.20% 71.34%
+system.physmem.bytesPerActivate::768-895 53 1.76% 73.10%
+system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67%
+system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00%
+system.physmem.bytesPerActivate::total 3004
+system.physmem.rdPerTurnAround::samples 3
+system.physmem.rdPerTurnAround::mean 6161.333333
+system.physmem.rdPerTurnAround::gmean 2123.401593
+system.physmem.rdPerTurnAround::stdev 8586.829993
+system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33%
+system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67%
+system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00%
+system.physmem.rdPerTurnAround::total 3
+system.physmem.wrPerTurnAround::samples 3
+system.physmem.wrPerTurnAround::mean 17.333333
+system.physmem.wrPerTurnAround::gmean 17.306995
+system.physmem.wrPerTurnAround::stdev 1.154701
+system.physmem.wrPerTurnAround::16 1 33.33% 33.33%
+system.physmem.wrPerTurnAround::18 2 66.67% 100.00%
+system.physmem.wrPerTurnAround::total 3
+system.physmem.totQLat 837911216
+system.physmem.totMemAccLat 1184598716
+system.physmem.totBusLat 92450000
+system.physmem.avgQLat 45316.99
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 64066.99
+system.physmem.avgRdBW 20.22
+system.physmem.avgWrBW 0.06
+system.physmem.avgRdBWSys 20.28
+system.physmem.avgWrBWSys 0.08
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.16
+system.physmem.busUtilRead 0.16
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.04
+system.physmem.avgWrQLen 13.38
+system.physmem.readRowHits 15512
+system.physmem.writeRowHits 18
+system.physmem.readRowHitRate 83.89
+system.physmem.writeRowHitRate 25.71
+system.physmem.avgGap 3142915.01
+system.physmem.pageHitRate 83.67
+system.physmem_0.actEnergy 16243500
+system.physmem_0.preEnergy 8614650
+system.physmem_0.readEnergy 75484080
+system.physmem_0.writeEnergy 156600
+system.physmem_0.refreshEnergy 1895549760.000000
+system.physmem_0.actBackEnergy 464945010
+system.physmem_0.preBackEnergy 99199680
+system.physmem_0.actPowerDownEnergy 4173482430
+system.physmem_0.prePowerDownEnergy 3272736480
+system.physmem_0.selfRefreshEnergy 9883191315
+system.physmem_0.totalEnergy 19894073865
+system.physmem_0.averagePower 339.947098
+system.physmem_0.totalIdleTime 57233116090
+system.physmem_0.memoryStateTime::IDLE 194944250
+system.physmem_0.memoryStateTime::REF 806364000
+system.physmem_0.memoryStateTime::SREF 39558059500
+system.physmem_0.memoryStateTime::PRE_PDN 8522710566
+system.physmem_0.memoryStateTime::ACT 286661660
+system.physmem_0.memoryStateTime::ACT_PDN 9152346024
+system.physmem_1.actEnergy 5255040
+system.physmem_1.preEnergy 2785530
+system.physmem_1.readEnergy 56527380
+system.physmem_1.writeEnergy 114840
+system.physmem_1.refreshEnergy 247699920.000000
+system.physmem_1.actBackEnergy 125328180
+system.physmem_1.preBackEnergy 13397280
+system.physmem_1.actPowerDownEnergy 772336890
+system.physmem_1.prePowerDownEnergy 242624160
+system.physmem_1.selfRefreshEnergy 13451278005
+system.physmem_1.totalEnergy 14917407225
+system.physmem_1.averagePower 254.906533
+system.physmem_1.totalIdleTime 58211272096
+system.physmem_1.memoryStateTime::IDLE 21634250
+system.physmem_1.memoryStateTime::REF 105218000
+system.physmem_1.memoryStateTime::SREF 55885668250
+system.physmem_1.memoryStateTime::PRE_PDN 631842954
+system.physmem_1.memoryStateTime::ACT 182961654
+system.physmem_1.memoryStateTime::ACT_PDN 1693760892
+system.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.branchPred.lookups 28121660
+system.cpu.branchPred.condPredicted 23134709
+system.cpu.branchPred.condIncorrect 844714
+system.cpu.branchPred.BTBLookups 11731332
+system.cpu.branchPred.BTBHits 11630363
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 99.139322
+system.cpu.branchPred.usedRAS 80725
+system.cpu.branchPred.RASInCorrect 95
+system.cpu.branchPred.indirectLookups 28301
+system.cpu.branchPred.indirectHits 25845
+system.cpu.branchPred.indirectMisses 2456
+system.cpu.branchPredindirectMispredicted 243
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 442
+system.cpu.pwrStateResidencyTicks::ON 58521086000
+system.cpu.numCycles 117042173
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 755365
+system.cpu.fetch.Insts 134380549
+system.cpu.fetch.Branches 28121660
+system.cpu.fetch.predictedBranches 11736933
+system.cpu.fetch.Cycles 115370240
+system.cpu.fetch.SquashCycles 1692792
+system.cpu.fetch.MiscStallCycles 848
+system.cpu.fetch.IcacheWaitRetryStallCycles 1033
+system.cpu.fetch.CacheLines 32086744
+system.cpu.fetch.IcacheSquashes 572
+system.cpu.fetch.rateDist::samples 116973882
+system.cpu.fetch.rateDist::mean 1.154260
+system.cpu.fetch.rateDist::stdev 1.318237
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 59688776 51.03% 51.03%
+system.cpu.fetch.rateDist::1 13868271 11.86% 62.88%
+system.cpu.fetch.rateDist::2 9100495 7.78% 70.66%
+system.cpu.fetch.rateDist::3 34316340 29.34% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 3
+system.cpu.fetch.rateDist::total 116973882
+system.cpu.fetch.branchRate 0.240269
+system.cpu.fetch.rate 1.148138
+system.cpu.decode.IdleCycles 8865418
+system.cpu.decode.BlockedCycles 65026599
+system.cpu.decode.RunCycles 32710680
+system.cpu.decode.UnblockCycles 9589004
+system.cpu.decode.SquashCycles 782181
+system.cpu.decode.BranchResolved 9831266
+system.cpu.decode.BranchMispred 64876
+system.cpu.decode.DecodedInsts 113761457
+system.cpu.decode.SquashedInsts 2108425
+system.cpu.rename.SquashCycles 782181
+system.cpu.rename.IdleCycles 15316274
+system.cpu.rename.BlockCycles 50229704
+system.cpu.rename.serializeStallCycles 114341
+system.cpu.rename.RunCycles 35119945
+system.cpu.rename.UnblockCycles 15411437
+system.cpu.rename.RenamedInsts 110456918
+system.cpu.rename.SquashedInsts 1289549
+system.cpu.rename.ROBFullEvents 11149602
+system.cpu.rename.IQFullEvents 1576334
+system.cpu.rename.LQFullEvents 2138216
+system.cpu.rename.SQFullEvents 510190
+system.cpu.rename.RenamedOperands 129202611
+system.cpu.rename.RenameLookups 481340709
+system.cpu.rename.int_rename_lookups 118978784
+system.cpu.rename.fp_rename_lookups 633
+system.cpu.rename.CommittedMaps 107312919
+system.cpu.rename.UndoneMaps 21889692
+system.cpu.rename.serializingInsts 4408
+system.cpu.rename.tempSerializingInsts 4400
+system.cpu.rename.skidInsts 21529051
+system.cpu.memDep0.insertedLoads 26813393
+system.cpu.memDep0.insertedStores 5308956
+system.cpu.memDep0.conflictingLoads 540635
+system.cpu.memDep0.conflictingStores 272789
+system.cpu.iq.iqInstsAdded 109383305
+system.cpu.iq.iqNonSpecInstsAdded 8282
+system.cpu.iq.iqInstsIssued 101253910
+system.cpu.iq.iqSquashedInstsIssued 993650
+system.cpu.iq.iqSquashedInstsExamined 18350556
+system.cpu.iq.iqSquashedOperandsExamined 40868291
+system.cpu.iq.iqSquashedNonSpecRemoved 64
+system.cpu.iq.issued_per_cycle::samples 116973882
+system.cpu.iq.issued_per_cycle::mean 0.865611
+system.cpu.iq.issued_per_cycle::stdev 0.989909
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45%
+system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13%
+system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89%
+system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97%
+system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00%
+system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 5
+system.cpu.iq.issued_per_cycle::total 116973882
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84%
+system.cpu.iq.fu_full::IntMult 51 0.00% 48.84%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54%
+system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00%
+system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00%
+system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93%
+system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94%
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99%
+system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00%
+system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00%
+system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::total 101253910
+system.cpu.iq.rate 0.865106
+system.cpu.iq.fu_busy_cnt 20139291
+system.cpu.iq.fu_busy_rate 0.198899
+system.cpu.iq.int_inst_queue_reads 340613998
+system.cpu.iq.int_inst_queue_writes 127742532
+system.cpu.iq.int_inst_queue_wakeup_accesses 99568159
+system.cpu.iq.fp_inst_queue_reads 645
+system.cpu.iq.fp_inst_queue_writes 896
+system.cpu.iq.fp_inst_queue_wakeup_accesses 147
+system.cpu.iq.int_alu_accesses 121392865
+system.cpu.iq.fp_alu_accesses 336
+system.cpu.iew.lsq.thread0.forwLoads 289487
+system.cpu.iew.lsq.thread0.invAddrLoads 0
+system.cpu.iew.lsq.thread0.squashedLoads 4337482
+system.cpu.iew.lsq.thread0.ignoredResponses 2085
+system.cpu.iew.lsq.thread0.memOrderViolation 1323
+system.cpu.iew.lsq.thread0.squashedStores 564112
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu.iew.lsq.thread0.blockedLoads 0
+system.cpu.iew.lsq.thread0.rescheduledLoads 7586
+system.cpu.iew.lsq.thread0.cacheBlocked 131115
+system.cpu.iew.iewIdleCycles 0
+system.cpu.iew.iewSquashCycles 782181
+system.cpu.iew.iewBlockCycles 8303656
+system.cpu.iew.iewUnblockCycles 706645
+system.cpu.iew.iewDispatchedInsts 109404410
+system.cpu.iew.iewDispSquashedInsts 0
+system.cpu.iew.iewDispLoadInsts 26813393
+system.cpu.iew.iewDispStoreInsts 5308956
+system.cpu.iew.iewDispNonSpecInsts 4394
+system.cpu.iew.iewIQFullEvents 183005
+system.cpu.iew.iewLSQFullEvents 362995
+system.cpu.iew.memOrderViolationEvents 1323
+system.cpu.iew.predictedTakenIncorrect 354101
+system.cpu.iew.predictedNotTakenIncorrect 451870
+system.cpu.iew.branchMispredicts 805971
+system.cpu.iew.iewExecutedInsts 100068536
+system.cpu.iew.iewExecLoadInsts 23799476
+system.cpu.iew.iewExecSquashedInsts 1185374
+system.cpu.iew.exec_swp 0
+system.cpu.iew.exec_nop 12823
+system.cpu.iew.exec_refs 28747002
+system.cpu.iew.exec_branches 20644390
+system.cpu.iew.exec_stores 4947526
+system.cpu.iew.exec_rate 0.854978
+system.cpu.iew.wb_sent 99653444
+system.cpu.iew.wb_count 99568306
+system.cpu.iew.wb_producers 59603520
+system.cpu.iew.wb_consumers 95472454
+system.cpu.iew.wb_rate 0.850705
+system.cpu.iew.wb_fanout 0.624301
+system.cpu.commit.commitSquashedInsts 17204380
+system.cpu.commit.commitNonSpecStalls 8218
+system.cpu.commit.branchMispredicts 780499
+system.cpu.commit.committed_per_cycle::samples 114317449
+system.cpu.commit.committed_per_cycle::mean 0.796498
+system.cpu.commit.committed_per_cycle::stdev 1.736161
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21%
+system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44%
+system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68%
+system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69%
+system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13%
+system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61%
+system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22%
+system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38%
+system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00%
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.commit.committed_per_cycle::min_value 0
+system.cpu.commit.committed_per_cycle::max_value 8
+system.cpu.commit.committed_per_cycle::total 114317449
+system.cpu.commit.committedInsts 90602408
+system.cpu.commit.committedOps 91053639
+system.cpu.commit.swp_count 0
+system.cpu.commit.refs 27220755
+system.cpu.commit.loads 22475911
+system.cpu.commit.membars 3888
+system.cpu.commit.branches 18732305
+system.cpu.commit.fp_insts 48
+system.cpu.commit.int_insts 72326352
+system.cpu.commit.function_calls 56148
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09%
+system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10%
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79%
+system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00%
+system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00%
+system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.commit.op_class_0::total 91053639
+system.cpu.commit.bw_lim_events 4142947
+system.cpu.rob.rob_reads 218426787
+system.cpu.rob.rob_writes 219173123
+system.cpu.timesIdled 593
+system.cpu.idleCycles 68291
+system.cpu.committedInsts 90589799
+system.cpu.committedOps 91041030
+system.cpu.cpi 1.292002
+system.cpu.cpi_total 1.292002
+system.cpu.ipc 0.773993
+system.cpu.ipc_total 0.773993
+system.cpu.int_regfile_reads 108095256
+system.cpu.int_regfile_writes 58597145
+system.cpu.fp_regfile_reads 58
+system.cpu.fp_regfile_writes 127
+system.cpu.cc_regfile_reads 368871207
+system.cpu.cc_regfile_writes 58517884
+system.cpu.misc_regfile_reads 28439348
+system.cpu.misc_regfile_writes 7784
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.tags.replacements 5470632
+system.cpu.dcache.tags.tagsinuse 511.768178
+system.cpu.dcache.tags.total_refs 18243100
+system.cpu.dcache.tags.sampled_refs 5471144
+system.cpu.dcache.tags.avg_refs 3.334421
+system.cpu.dcache.tags.warmup_cycle 38187500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999547
+system.cpu.dcache.tags.occ_percent::total 0.999547
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 327
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 185
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 61896540
+system.cpu.dcache.tags.data_accesses 61896540
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.ReadReq_hits::cpu.data 13880582
+system.cpu.dcache.ReadReq_hits::total 13880582
+system.cpu.dcache.WriteReq_hits::cpu.data 4354214
+system.cpu.dcache.WriteReq_hits::total 4354214
+system.cpu.dcache.SoftPFReq_hits::cpu.data 522
+system.cpu.dcache.SoftPFReq_hits::total 522
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873
+system.cpu.dcache.LoadLockedReq_hits::total 3873
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887
+system.cpu.dcache.StoreCondReq_hits::total 3887
+system.cpu.dcache.demand_hits::cpu.data 18234796
+system.cpu.dcache.demand_hits::total 18234796
+system.cpu.dcache.overall_hits::cpu.data 18235318
+system.cpu.dcache.overall_hits::total 18235318
+system.cpu.dcache.ReadReq_misses::cpu.data 9588832
+system.cpu.dcache.ReadReq_misses::total 9588832
+system.cpu.dcache.WriteReq_misses::cpu.data 380767
+system.cpu.dcache.WriteReq_misses::total 380767
+system.cpu.dcache.SoftPFReq_misses::cpu.data 7
+system.cpu.dcache.SoftPFReq_misses::total 7
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 14
+system.cpu.dcache.LoadLockedReq_misses::total 14
+system.cpu.dcache.demand_misses::cpu.data 9969599
+system.cpu.dcache.demand_misses::total 9969599
+system.cpu.dcache.overall_misses::cpu.data 9969606
+system.cpu.dcache.overall_misses::total 9969606
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500
+system.cpu.dcache.ReadReq_miss_latency::total 89393317500
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083
+system.cpu.dcache.WriteReq_miss_latency::total 4103772083
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 302000
+system.cpu.dcache.demand_miss_latency::cpu.data 93497089583
+system.cpu.dcache.demand_miss_latency::total 93497089583
+system.cpu.dcache.overall_miss_latency::cpu.data 93497089583
+system.cpu.dcache.overall_miss_latency::total 93497089583
+system.cpu.dcache.ReadReq_accesses::cpu.data 23469414
+system.cpu.dcache.ReadReq_accesses::total 23469414
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981
+system.cpu.dcache.WriteReq_accesses::total 4734981
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 529
+system.cpu.dcache.SoftPFReq_accesses::total 529
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
+system.cpu.dcache.LoadLockedReq_accesses::total 3887
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887
+system.cpu.dcache.StoreCondReq_accesses::total 3887
+system.cpu.dcache.demand_accesses::cpu.data 28204395
+system.cpu.dcache.demand_accesses::total 28204395
+system.cpu.dcache.overall_accesses::cpu.data 28204924
+system.cpu.dcache.overall_accesses::total 28204924
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567
+system.cpu.dcache.ReadReq_miss_rate::total 0.408567
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416
+system.cpu.dcache.WriteReq_miss_rate::total 0.080416
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602
+system.cpu.dcache.demand_miss_rate::cpu.data 0.353477
+system.cpu.dcache.demand_miss_rate::total 0.353477
+system.cpu.dcache.overall_miss_rate::cpu.data 0.353470
+system.cpu.dcache.overall_miss_rate::total 0.353470
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255
+system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684
+system.cpu.dcache.demand_avg_miss_latency::total 9378.219684
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099
+system.cpu.dcache.overall_avg_miss_latency::total 9378.213099
+system.cpu.dcache.blocked_cycles::no_mshrs 331670
+system.cpu.dcache.blocked_cycles::no_targets 131340
+system.cpu.dcache.blocked::no_mshrs 121646
+system.cpu.dcache.blocked::no_targets 12838
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518
+system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566
+system.cpu.dcache.writebacks::writebacks 5470632
+system.cpu.dcache.writebacks::total 5470632
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269
+system.cpu.dcache.ReadReq_mshr_hits::total 4340269
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185
+system.cpu.dcache.WriteReq_mshr_hits::total 158185
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14
+system.cpu.dcache.demand_mshr_hits::cpu.data 4498454
+system.cpu.dcache.demand_mshr_hits::total 4498454
+system.cpu.dcache.overall_mshr_hits::cpu.data 4498454
+system.cpu.dcache.overall_mshr_hits::total 4498454
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563
+system.cpu.dcache.ReadReq_mshr_misses::total 5248563
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582
+system.cpu.dcache.WriteReq_mshr_misses::total 222582
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4
+system.cpu.dcache.SoftPFReq_mshr_misses::total 4
+system.cpu.dcache.demand_mshr_misses::cpu.data 5471145
+system.cpu.dcache.demand_mshr_misses::total 5471145
+system.cpu.dcache.overall_mshr_misses::cpu.data 5471149
+system.cpu.dcache.overall_mshr_misses::total 5471149
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983
+system.cpu.dcache.demand_mshr_miss_latency::total 46120568983
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483
+system.cpu.dcache.overall_mshr_miss_latency::total 46120804483
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982
+system.cpu.dcache.demand_mshr_miss_rate::total 0.193982
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979
+system.cpu.dcache.overall_mshr_miss_rate::total 0.193979
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.tags.replacements 449
+system.cpu.icache.tags.tagsinuse 426.857560
+system.cpu.icache.tags.total_refs 32085580
+system.cpu.icache.tags.sampled_refs 907
+system.cpu.icache.tags.avg_refs 35375.501654
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560
+system.cpu.icache.tags.occ_percent::cpu.inst 0.833706
+system.cpu.icache.tags.occ_percent::total 0.833706
+system.cpu.icache.tags.occ_task_id_blocks::1024 458
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53
+system.cpu.icache.tags.age_task_id_blocks_1024::2 50
+system.cpu.icache.tags.age_task_id_blocks_1024::3 22
+system.cpu.icache.tags.age_task_id_blocks_1024::4 333
+system.cpu.icache.tags.occ_task_id_percent::1024 0.894531
+system.cpu.icache.tags.tag_accesses 64174375
+system.cpu.icache.tags.data_accesses 64174375
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.ReadReq_hits::cpu.inst 32085580
+system.cpu.icache.ReadReq_hits::total 32085580
+system.cpu.icache.demand_hits::cpu.inst 32085580
+system.cpu.icache.demand_hits::total 32085580
+system.cpu.icache.overall_hits::cpu.inst 32085580
+system.cpu.icache.overall_hits::total 32085580
+system.cpu.icache.ReadReq_misses::cpu.inst 1154
+system.cpu.icache.ReadReq_misses::total 1154
+system.cpu.icache.demand_misses::cpu.inst 1154
+system.cpu.icache.demand_misses::total 1154
+system.cpu.icache.overall_misses::cpu.inst 1154
+system.cpu.icache.overall_misses::total 1154
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480
+system.cpu.icache.ReadReq_miss_latency::total 81624480
+system.cpu.icache.demand_miss_latency::cpu.inst 81624480
+system.cpu.icache.demand_miss_latency::total 81624480
+system.cpu.icache.overall_miss_latency::cpu.inst 81624480
+system.cpu.icache.overall_miss_latency::total 81624480
+system.cpu.icache.ReadReq_accesses::cpu.inst 32086734
+system.cpu.icache.ReadReq_accesses::total 32086734
+system.cpu.icache.demand_accesses::cpu.inst 32086734
+system.cpu.icache.demand_accesses::total 32086734
+system.cpu.icache.overall_accesses::cpu.inst 32086734
+system.cpu.icache.overall_accesses::total 32086734
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036
+system.cpu.icache.ReadReq_miss_rate::total 0.000036
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000036
+system.cpu.icache.demand_miss_rate::total 0.000036
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000036
+system.cpu.icache.overall_miss_rate::total 0.000036
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.demand_avg_miss_latency::total 70731.785095
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.overall_avg_miss_latency::total 70731.785095
+system.cpu.icache.blocked_cycles::no_mshrs 21770
+system.cpu.icache.blocked_cycles::no_targets 1853
+system.cpu.icache.blocked::no_mshrs 229
+system.cpu.icache.blocked::no_targets 7
+system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502
+system.cpu.icache.avg_blocked_cycles::no_targets 264.714286
+system.cpu.icache.writebacks::writebacks 449
+system.cpu.icache.writebacks::total 449
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246
+system.cpu.icache.ReadReq_mshr_hits::total 246
+system.cpu.icache.demand_mshr_hits::cpu.inst 246
+system.cpu.icache.demand_mshr_hits::total 246
+system.cpu.icache.overall_mshr_hits::cpu.inst 246
+system.cpu.icache.overall_mshr_hits::total 246
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908
+system.cpu.icache.ReadReq_mshr_misses::total 908
+system.cpu.icache.demand_mshr_misses::cpu.inst 908
+system.cpu.icache.demand_mshr_misses::total 908
+system.cpu.icache.overall_mshr_misses::cpu.inst 908
+system.cpu.icache.overall_mshr_misses::total 908
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.demand_mshr_miss_latency::total 61609984
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.overall_mshr_miss_latency::total 61609984
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.demand_mshr_miss_rate::total 0.000028
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.overall_mshr_miss_rate::total 0.000028
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667
+system.cpu.l2cache.prefetcher.pfIdentified 5295978
+system.cpu.l2cache.prefetcher.pfBufferHit 268023
+system.cpu.l2cache.prefetcher.pfInCache 0
+system.cpu.l2cache.prefetcher.pfRemovedFull 0
+system.cpu.l2cache.prefetcher.pfSpanPage 14076270
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.tags.replacements 99
+system.cpu.l2cache.tags.tagsinuse 11218.637670
+system.cpu.l2cache.tags.total_refs 5292117
+system.cpu.l2cache.tags.sampled_refs 14656
+system.cpu.l2cache.tags.avg_refs 361.088769
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012
+system.cpu.l2cache.tags.occ_percent::writebacks 0.680659
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072
+system.cpu.l2cache.tags.occ_percent::total 0.684731
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 67
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399
+system.cpu.l2cache.tags.tag_accesses 180525307
+system.cpu.l2cache.tags.data_accesses 180525307
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_hits::total 5460197
+system.cpu.l2cache.WritebackClean_hits::writebacks 7956
+system.cpu.l2cache.WritebackClean_hits::total 7956
+system.cpu.l2cache.ReadExReq_hits::cpu.data 225753
+system.cpu.l2cache.ReadExReq_hits::total 225753
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207
+system.cpu.l2cache.ReadCleanReq_hits::total 207
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769
+system.cpu.l2cache.ReadSharedReq_hits::total 5241769
+system.cpu.l2cache.demand_hits::cpu.inst 207
+system.cpu.l2cache.demand_hits::cpu.data 5467522
+system.cpu.l2cache.demand_hits::total 5467729
+system.cpu.l2cache.overall_hits::cpu.inst 207
+system.cpu.l2cache.overall_hits::cpu.data 5467522
+system.cpu.l2cache.overall_hits::total 5467729
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_misses::total 5
+system.cpu.l2cache.ReadExReq_misses::cpu.data 499
+system.cpu.l2cache.ReadExReq_misses::total 499
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701
+system.cpu.l2cache.ReadCleanReq_misses::total 701
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123
+system.cpu.l2cache.ReadSharedReq_misses::total 3123
+system.cpu.l2cache.demand_misses::cpu.inst 701
+system.cpu.l2cache.demand_misses::cpu.data 3622
+system.cpu.l2cache.demand_misses::total 4323
+system.cpu.l2cache.overall_misses::cpu.inst 701
+system.cpu.l2cache.overall_misses::cpu.data 3622
+system.cpu.l2cache.overall_misses::total 4323
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500
+system.cpu.l2cache.UpgradeReq_miss_latency::total 105500
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000
+system.cpu.l2cache.ReadExReq_miss_latency::total 66196000
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.demand_miss_latency::cpu.data 683496000
+system.cpu.l2cache.demand_miss_latency::total 742803500
+system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.overall_miss_latency::cpu.data 683496000
+system.cpu.l2cache.overall_miss_latency::total 742803500
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_accesses::total 5460197
+system.cpu.l2cache.WritebackClean_accesses::writebacks 7956
+system.cpu.l2cache.WritebackClean_accesses::total 7956
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_accesses::total 5
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252
+system.cpu.l2cache.ReadExReq_accesses::total 226252
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908
+system.cpu.l2cache.ReadCleanReq_accesses::total 908
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892
+system.cpu.l2cache.ReadSharedReq_accesses::total 5244892
+system.cpu.l2cache.demand_accesses::cpu.inst 908
+system.cpu.l2cache.demand_accesses::cpu.data 5471144
+system.cpu.l2cache.demand_accesses::total 5472052
+system.cpu.l2cache.overall_accesses::cpu.inst 908
+system.cpu.l2cache.overall_accesses::cpu.data 5471144
+system.cpu.l2cache.overall_accesses::total 5472052
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.demand_miss_rate::total 0.000790
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.overall_miss_rate::total 0.000790
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.unused_prefetches 1
+system.cpu.l2cache.writebacks::writebacks 74
+system.cpu.l2cache.writebacks::total 74
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158
+system.cpu.l2cache.ReadExReq_mshr_hits::total 158
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1
+system.cpu.l2cache.demand_mshr_hits::cpu.data 180
+system.cpu.l2cache.demand_mshr_hits::total 181
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1
+system.cpu.l2cache.overall_mshr_hits::cpu.data 180
+system.cpu.l2cache.overall_mshr_hits::total 181
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.HardPFReq_mshr_misses::total 316332
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 5
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341
+system.cpu.l2cache.ReadExReq_mshr_misses::total 341
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 700
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3442
+system.cpu.l2cache.demand_mshr_misses::total 4142
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 700
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3442
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.overall_mshr_misses::total 320474
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.demand_mshr_miss_latency::total 692500000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441
+system.cpu.toL2Bus.snoop_filter.tot_requests 10943138
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928
+system.cpu.toL2Bus.snoop_filter.tot_snoops 301927
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.toL2Bus.trans_dist::ReadResp 5245799
+system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271
+system.cpu.toL2Bus.trans_dist::WritebackClean 10884
+system.cpu.toL2Bus.trans_dist::CleanEvict 25
+system.cpu.toL2Bus.trans_dist::HardPFReq 318221
+system.cpu.toL2Bus.trans_dist::HardPFResp 6
+system.cpu.toL2Bus.trans_dist::UpgradeReq 5
+system.cpu.toL2Bus.trans_dist::UpgradeResp 5
+system.cpu.toL2Bus.trans_dist::ReadExReq 226252
+system.cpu.toL2Bus.trans_dist::ReadExResp 226252
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 908
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936
+system.cpu.toL2Bus.pkt_count::total 16415200
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048
+system.cpu.toL2Bus.pkt_size::total 700360832
+system.cpu.toL2Bus.snoops 318326
+system.cpu.toL2Bus.snoopTraffic 5120
+system.cpu.toL2Bus.snoop_fanout::samples 5790377
+system.cpu.toL2Bus.snoop_fanout::mean 0.052651
+system.cpu.toL2Bus.snoop_fanout::stdev 0.223337
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73%
+system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 5790377
+system.cpu.toL2Bus.reqLayer0.occupancy 10942650026
+system.cpu.toL2Bus.reqLayer0.utilization 18.7
+system.cpu.toL2Bus.snoopLayer0.occupancy 9032
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 1362995
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 8206721993
+system.cpu.toL2Bus.respLayer1.utilization 14.0
+system.membus.snoop_filter.tot_requests 18651
+system.membus.snoop_filter.hit_single_requests 3037
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.membus.trans_dist::ReadResp 18205
+system.membus.trans_dist::WritebackDirty 74
+system.membus.trans_dist::CleanEvict 25
+system.membus.trans_dist::UpgradeReq 6
+system.membus.trans_dist::ReadExReq 340
+system.membus.trans_dist::ReadExResp 340
+system.membus.trans_dist::ReadSharedReq 18206
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196
+system.membus.pkt_count::total 37196
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616
+system.membus.pkt_size::total 1191616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 18552
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 18552
+system.membus.reqLayer0.occupancy 29380556
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff