---------- Begin Simulation Statistics ----------
-sim_seconds 0.028553 # Number of seconds simulated
-sim_ticks 28553466500 # Number of ticks simulated
-final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181848 # Simulator instruction rate (inst/s)
-host_op_rate 183154 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57311644 # Simulator tick rate (ticks/s)
-host_mem_usage 367800 # Number of bytes of host memory used
-host_seconds 498.21 # Real time elapsed on the host
-sim_insts 90599368 # Number of instructions simulated
-sim_ops 91249921 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 57106934 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued
-system.cpu.iq.rate 1.850751 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 36382 # number of nop insts executed
-system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21352915 # Number of branches executed
-system.cpu.iew.exec_stores 5076392 # Number of stores executed
-system.cpu.iew.exec_rate 1.832232 # Inst execution rate
-system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 61949538 # num instructions producing a value
-system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 90611977 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 91262530 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 706178 1.33% 88.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 261507 0.49% 90.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5166197 9.75% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 52991397 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90611977 # Number of instructions committed
-system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27322638 # Number of memory references committed
-system.cpu.commit.loads 22575880 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18722474 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72533330 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5166197 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 167023568 # The number of ROB reads
-system.cpu.rob.rob_writes 242480145 # The number of ROB writes
-system.cpu.timesIdled 16985 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64617 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90599368 # Number of Instructions Simulated
-system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated
-system.cpu.cpi 0.630324 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.630324 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.586486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.586486 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 497500268 # number of integer regfile reads
-system.cpu.int_regfile_writes 120842597 # number of integer regfile writes
-system.cpu.fp_regfile_reads 229 # number of floating regfile reads
-system.cpu.fp_regfile_writes 593 # number of floating regfile writes
-system.cpu.misc_regfile_reads 183620284 # number of misc regfile reads
-system.cpu.misc_regfile_writes 11612 # number of misc regfile writes
-system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 638.455928 # Cycle average of tags in use
-system.cpu.icache.total_refs 14143171 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 734 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 19268.625341 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 638.455928 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.311746 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.311746 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 14143171 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 14143171 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 14143171 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 14143171 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 14143171 # number of overall hits
-system.cpu.icache.overall_hits::total 14143171 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses
-system.cpu.icache.overall_misses::total 967 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 35020500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 35020500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 35020500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 35020500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 35020500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 35020500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 14144138 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 14144138 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 14144138 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 14144138 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 14144138 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 14144138 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000068 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000068 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000068 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36215.615305 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36215.615305 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 233 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 233 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 233 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 233 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 233 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26444000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 26444000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26444000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 26444000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26444000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 26444000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943512 # number of replacements
-system.cpu.dcache.tagsinuse 3689.791275 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28381642 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.950826 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8154700000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3689.791275 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.900828 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.900828 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 23801988 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23801988 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4567984 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4567984 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 5869 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 5869 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 28369972 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 28369972 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 28369972 # number of overall hits
-system.cpu.dcache.overall_hits::total 28369972 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1060525 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1060525 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 166997 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 166997 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1227522 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1227522 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1227522 # number of overall misses
-system.cpu.dcache.overall_misses::total 1227522 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 21965060500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 21965060500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 6217004264 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 6217004264 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 153500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 153500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 28182064764 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 28182064764 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28182064764 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28182064764 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24862513 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24862513 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5877 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 5877 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 29597494 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 29597494 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 29597494 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 29597494 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042656 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.042656 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.035269 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001361 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001361 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22958.500755 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22958.500755 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 78852438 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9147 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 8620.579206 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942869 # number of writebacks
-system.cpu.dcache.writebacks::total 942869 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148009 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 148009 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131905 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 131905 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 279914 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 279914 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 279914 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 279914 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912516 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 912516 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35092 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 35092 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 947608 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 947608 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 947608 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 947608 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16755802500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 16755802500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751499399 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751499399 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18507301899 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 18507301899 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18507301899 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 18507301899 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036702 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036702 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007411 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007411 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032016 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032016 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 10958.956435 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1839863 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 15497 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 118.723818 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 10102.128367 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 622.173685 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 234.654384 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.308292 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.018987 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.007161 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.334441 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 912088 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 912112 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 942869 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 942869 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 20704 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 20704 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 932792 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 932816 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 932792 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932816 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 710 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 14535 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 14535 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 710 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 15526 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 710 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses
-system.cpu.l2cache.overall_misses::total 15526 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25363000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10310000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 35673000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499681500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 499681500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 25363000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 509991500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 535354500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 25363000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 509991500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 535354500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 734 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 912369 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 913103 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942869 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942869 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 35239 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 35239 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 734 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 734 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967302 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001085 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412469 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.412469 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967302 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015635 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016372 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967302 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015635 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016372 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35722.535211 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36690.391459 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35996.972755 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34377.812178 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34377.812178 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34481.160634 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34481.160634 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 708 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 708 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 708 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23086000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9134000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32220000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453439000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453439000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23086000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462573000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 485659000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23086000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462573000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 485659000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412469 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412469 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+sim_seconds 0.058521
+sim_ticks 58521086000
+final_tick 58521086000
+sim_freq 1000000000000
+host_inst_rate 103970
+host_op_rate 104488
+host_tick_rate 67164623
+host_mem_usage 503044
+host_seconds 871.31
+sim_insts 90589799
+sim_ops 91041030
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.physmem.bytes_read::cpu.inst 44736
+system.physmem.bytes_read::cpu.data 220224
+system.physmem.bytes_read::cpu.l2cache.prefetcher 921920
+system.physmem.bytes_read::total 1186880
+system.physmem.bytes_inst_read::cpu.inst 44736
+system.physmem.bytes_inst_read::total 44736
+system.physmem.bytes_written::writebacks 4736
+system.physmem.bytes_written::total 4736
+system.physmem.num_reads::cpu.inst 699
+system.physmem.num_reads::cpu.data 3441
+system.physmem.num_reads::cpu.l2cache.prefetcher 14405
+system.physmem.num_reads::total 18545
+system.physmem.num_writes::writebacks 74
+system.physmem.num_writes::total 74
+system.physmem.bw_read::cpu.inst 764442
+system.physmem.bw_read::cpu.data 3763156
+system.physmem.bw_read::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_read::total 20281237
+system.physmem.bw_inst_read::cpu.inst 764442
+system.physmem.bw_inst_read::total 764442
+system.physmem.bw_write::writebacks 80928
+system.physmem.bw_write::total 80928
+system.physmem.bw_total::writebacks 80928
+system.physmem.bw_total::cpu.inst 764442
+system.physmem.bw_total::cpu.data 3763156
+system.physmem.bw_total::cpu.l2cache.prefetcher 15753638
+system.physmem.bw_total::total 20362165
+system.physmem.readReqs 18546
+system.physmem.writeReqs 74
+system.physmem.readBursts 18546
+system.physmem.writeBursts 74
+system.physmem.bytesReadDRAM 1183360
+system.physmem.bytesReadWrQ 3584
+system.physmem.bytesWritten 3328
+system.physmem.bytesReadSys 1186944
+system.physmem.bytesWrittenSys 4736
+system.physmem.servicedByWrQ 56
+system.physmem.mergedWrBursts 4
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 3297
+system.physmem.perBankRdBursts::1 920
+system.physmem.perBankRdBursts::2 949
+system.physmem.perBankRdBursts::3 1031
+system.physmem.perBankRdBursts::4 1067
+system.physmem.perBankRdBursts::5 1119
+system.physmem.perBankRdBursts::6 1093
+system.physmem.perBankRdBursts::7 1097
+system.physmem.perBankRdBursts::8 1024
+system.physmem.perBankRdBursts::9 961
+system.physmem.perBankRdBursts::10 934
+system.physmem.perBankRdBursts::11 899
+system.physmem.perBankRdBursts::12 902
+system.physmem.perBankRdBursts::13 895
+system.physmem.perBankRdBursts::14 1399
+system.physmem.perBankRdBursts::15 903
+system.physmem.perBankWrBursts::0 1
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 2
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 1
+system.physmem.perBankWrBursts::5 14
+system.physmem.perBankWrBursts::6 9
+system.physmem.perBankWrBursts::7 3
+system.physmem.perBankWrBursts::8 1
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 2
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 1
+system.physmem.perBankWrBursts::13 12
+system.physmem.perBankWrBursts::14 5
+system.physmem.perBankWrBursts::15 1
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 58521077500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 18546
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 74
+system.physmem.rdQLenPdf::0 12593
+system.physmem.rdQLenPdf::1 3390
+system.physmem.rdQLenPdf::2 500
+system.physmem.rdQLenPdf::3 409
+system.physmem.rdQLenPdf::4 319
+system.physmem.rdQLenPdf::5 301
+system.physmem.rdQLenPdf::6 297
+system.physmem.rdQLenPdf::7 299
+system.physmem.rdQLenPdf::8 279
+system.physmem.rdQLenPdf::9 103
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 3
+system.physmem.wrQLenPdf::16 3
+system.physmem.wrQLenPdf::17 4
+system.physmem.wrQLenPdf::18 3
+system.physmem.wrQLenPdf::19 3
+system.physmem.wrQLenPdf::20 3
+system.physmem.wrQLenPdf::21 3
+system.physmem.wrQLenPdf::22 3
+system.physmem.wrQLenPdf::23 3
+system.physmem.wrQLenPdf::24 3
+system.physmem.wrQLenPdf::25 3
+system.physmem.wrQLenPdf::26 3
+system.physmem.wrQLenPdf::27 3
+system.physmem.wrQLenPdf::28 3
+system.physmem.wrQLenPdf::29 3
+system.physmem.wrQLenPdf::30 3
+system.physmem.wrQLenPdf::31 3
+system.physmem.wrQLenPdf::32 3
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 3004
+system.physmem.bytesPerActivate::mean 394.652463
+system.physmem.bytesPerActivate::gmean 214.589229
+system.physmem.bytesPerActivate::stdev 405.543781
+system.physmem.bytesPerActivate::0-127 893 29.73% 29.73%
+system.physmem.bytesPerActivate::128-255 965 32.12% 61.85%
+system.physmem.bytesPerActivate::256-383 89 2.96% 64.81%
+system.physmem.bytesPerActivate::384-511 63 2.10% 66.91%
+system.physmem.bytesPerActivate::512-639 67 2.23% 69.14%
+system.physmem.bytesPerActivate::640-767 66 2.20% 71.34%
+system.physmem.bytesPerActivate::768-895 53 1.76% 73.10%
+system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67%
+system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00%
+system.physmem.bytesPerActivate::total 3004
+system.physmem.rdPerTurnAround::samples 3
+system.physmem.rdPerTurnAround::mean 6161.333333
+system.physmem.rdPerTurnAround::gmean 2123.401593
+system.physmem.rdPerTurnAround::stdev 8586.829993
+system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33%
+system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67%
+system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00%
+system.physmem.rdPerTurnAround::total 3
+system.physmem.wrPerTurnAround::samples 3
+system.physmem.wrPerTurnAround::mean 17.333333
+system.physmem.wrPerTurnAround::gmean 17.306995
+system.physmem.wrPerTurnAround::stdev 1.154701
+system.physmem.wrPerTurnAround::16 1 33.33% 33.33%
+system.physmem.wrPerTurnAround::18 2 66.67% 100.00%
+system.physmem.wrPerTurnAround::total 3
+system.physmem.totQLat 837911216
+system.physmem.totMemAccLat 1184598716
+system.physmem.totBusLat 92450000
+system.physmem.avgQLat 45316.99
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 64066.99
+system.physmem.avgRdBW 20.22
+system.physmem.avgWrBW 0.06
+system.physmem.avgRdBWSys 20.28
+system.physmem.avgWrBWSys 0.08
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.16
+system.physmem.busUtilRead 0.16
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.04
+system.physmem.avgWrQLen 13.38
+system.physmem.readRowHits 15512
+system.physmem.writeRowHits 18
+system.physmem.readRowHitRate 83.89
+system.physmem.writeRowHitRate 25.71
+system.physmem.avgGap 3142915.01
+system.physmem.pageHitRate 83.67
+system.physmem_0.actEnergy 16243500
+system.physmem_0.preEnergy 8614650
+system.physmem_0.readEnergy 75484080
+system.physmem_0.writeEnergy 156600
+system.physmem_0.refreshEnergy 1895549760.000000
+system.physmem_0.actBackEnergy 464945010
+system.physmem_0.preBackEnergy 99199680
+system.physmem_0.actPowerDownEnergy 4173482430
+system.physmem_0.prePowerDownEnergy 3272736480
+system.physmem_0.selfRefreshEnergy 9883191315
+system.physmem_0.totalEnergy 19894073865
+system.physmem_0.averagePower 339.947098
+system.physmem_0.totalIdleTime 57233116090
+system.physmem_0.memoryStateTime::IDLE 194944250
+system.physmem_0.memoryStateTime::REF 806364000
+system.physmem_0.memoryStateTime::SREF 39558059500
+system.physmem_0.memoryStateTime::PRE_PDN 8522710566
+system.physmem_0.memoryStateTime::ACT 286661660
+system.physmem_0.memoryStateTime::ACT_PDN 9152346024
+system.physmem_1.actEnergy 5255040
+system.physmem_1.preEnergy 2785530
+system.physmem_1.readEnergy 56527380
+system.physmem_1.writeEnergy 114840
+system.physmem_1.refreshEnergy 247699920.000000
+system.physmem_1.actBackEnergy 125328180
+system.physmem_1.preBackEnergy 13397280
+system.physmem_1.actPowerDownEnergy 772336890
+system.physmem_1.prePowerDownEnergy 242624160
+system.physmem_1.selfRefreshEnergy 13451278005
+system.physmem_1.totalEnergy 14917407225
+system.physmem_1.averagePower 254.906533
+system.physmem_1.totalIdleTime 58211272096
+system.physmem_1.memoryStateTime::IDLE 21634250
+system.physmem_1.memoryStateTime::REF 105218000
+system.physmem_1.memoryStateTime::SREF 55885668250
+system.physmem_1.memoryStateTime::PRE_PDN 631842954
+system.physmem_1.memoryStateTime::ACT 182961654
+system.physmem_1.memoryStateTime::ACT_PDN 1693760892
+system.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.branchPred.lookups 28121660
+system.cpu.branchPred.condPredicted 23134709
+system.cpu.branchPred.condIncorrect 844714
+system.cpu.branchPred.BTBLookups 11731332
+system.cpu.branchPred.BTBHits 11630363
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 99.139322
+system.cpu.branchPred.usedRAS 80725
+system.cpu.branchPred.RASInCorrect 95
+system.cpu.branchPred.indirectLookups 28301
+system.cpu.branchPred.indirectHits 25845
+system.cpu.branchPred.indirectMisses 2456
+system.cpu.branchPredindirectMispredicted 243
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 442
+system.cpu.pwrStateResidencyTicks::ON 58521086000
+system.cpu.numCycles 117042173
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 755365
+system.cpu.fetch.Insts 134380549
+system.cpu.fetch.Branches 28121660
+system.cpu.fetch.predictedBranches 11736933
+system.cpu.fetch.Cycles 115370240
+system.cpu.fetch.SquashCycles 1692792
+system.cpu.fetch.MiscStallCycles 848
+system.cpu.fetch.IcacheWaitRetryStallCycles 1033
+system.cpu.fetch.CacheLines 32086744
+system.cpu.fetch.IcacheSquashes 572
+system.cpu.fetch.rateDist::samples 116973882
+system.cpu.fetch.rateDist::mean 1.154260
+system.cpu.fetch.rateDist::stdev 1.318237
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 59688776 51.03% 51.03%
+system.cpu.fetch.rateDist::1 13868271 11.86% 62.88%
+system.cpu.fetch.rateDist::2 9100495 7.78% 70.66%
+system.cpu.fetch.rateDist::3 34316340 29.34% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 3
+system.cpu.fetch.rateDist::total 116973882
+system.cpu.fetch.branchRate 0.240269
+system.cpu.fetch.rate 1.148138
+system.cpu.decode.IdleCycles 8865418
+system.cpu.decode.BlockedCycles 65026599
+system.cpu.decode.RunCycles 32710680
+system.cpu.decode.UnblockCycles 9589004
+system.cpu.decode.SquashCycles 782181
+system.cpu.decode.BranchResolved 9831266
+system.cpu.decode.BranchMispred 64876
+system.cpu.decode.DecodedInsts 113761457
+system.cpu.decode.SquashedInsts 2108425
+system.cpu.rename.SquashCycles 782181
+system.cpu.rename.IdleCycles 15316274
+system.cpu.rename.BlockCycles 50229704
+system.cpu.rename.serializeStallCycles 114341
+system.cpu.rename.RunCycles 35119945
+system.cpu.rename.UnblockCycles 15411437
+system.cpu.rename.RenamedInsts 110456918
+system.cpu.rename.SquashedInsts 1289549
+system.cpu.rename.ROBFullEvents 11149602
+system.cpu.rename.IQFullEvents 1576334
+system.cpu.rename.LQFullEvents 2138216
+system.cpu.rename.SQFullEvents 510190
+system.cpu.rename.RenamedOperands 129202611
+system.cpu.rename.RenameLookups 481340709
+system.cpu.rename.int_rename_lookups 118978784
+system.cpu.rename.fp_rename_lookups 633
+system.cpu.rename.CommittedMaps 107312919
+system.cpu.rename.UndoneMaps 21889692
+system.cpu.rename.serializingInsts 4408
+system.cpu.rename.tempSerializingInsts 4400
+system.cpu.rename.skidInsts 21529051
+system.cpu.memDep0.insertedLoads 26813393
+system.cpu.memDep0.insertedStores 5308956
+system.cpu.memDep0.conflictingLoads 540635
+system.cpu.memDep0.conflictingStores 272789
+system.cpu.iq.iqInstsAdded 109383305
+system.cpu.iq.iqNonSpecInstsAdded 8282
+system.cpu.iq.iqInstsIssued 101253910
+system.cpu.iq.iqSquashedInstsIssued 993650
+system.cpu.iq.iqSquashedInstsExamined 18350556
+system.cpu.iq.iqSquashedOperandsExamined 40868291
+system.cpu.iq.iqSquashedNonSpecRemoved 64
+system.cpu.iq.issued_per_cycle::samples 116973882
+system.cpu.iq.issued_per_cycle::mean 0.865611
+system.cpu.iq.issued_per_cycle::stdev 0.989909
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45%
+system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13%
+system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89%
+system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97%
+system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00%
+system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 5
+system.cpu.iq.issued_per_cycle::total 116973882
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84%
+system.cpu.iq.fu_full::IntMult 51 0.00% 48.84%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84%
+system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54%
+system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00%
+system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00%
+system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93%
+system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94%
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94%
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94%
+system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99%
+system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00%
+system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00%
+system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::total 101253910
+system.cpu.iq.rate 0.865106
+system.cpu.iq.fu_busy_cnt 20139291
+system.cpu.iq.fu_busy_rate 0.198899
+system.cpu.iq.int_inst_queue_reads 340613998
+system.cpu.iq.int_inst_queue_writes 127742532
+system.cpu.iq.int_inst_queue_wakeup_accesses 99568159
+system.cpu.iq.fp_inst_queue_reads 645
+system.cpu.iq.fp_inst_queue_writes 896
+system.cpu.iq.fp_inst_queue_wakeup_accesses 147
+system.cpu.iq.int_alu_accesses 121392865
+system.cpu.iq.fp_alu_accesses 336
+system.cpu.iew.lsq.thread0.forwLoads 289487
+system.cpu.iew.lsq.thread0.invAddrLoads 0
+system.cpu.iew.lsq.thread0.squashedLoads 4337482
+system.cpu.iew.lsq.thread0.ignoredResponses 2085
+system.cpu.iew.lsq.thread0.memOrderViolation 1323
+system.cpu.iew.lsq.thread0.squashedStores 564112
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0
+system.cpu.iew.lsq.thread0.blockedLoads 0
+system.cpu.iew.lsq.thread0.rescheduledLoads 7586
+system.cpu.iew.lsq.thread0.cacheBlocked 131115
+system.cpu.iew.iewIdleCycles 0
+system.cpu.iew.iewSquashCycles 782181
+system.cpu.iew.iewBlockCycles 8303656
+system.cpu.iew.iewUnblockCycles 706645
+system.cpu.iew.iewDispatchedInsts 109404410
+system.cpu.iew.iewDispSquashedInsts 0
+system.cpu.iew.iewDispLoadInsts 26813393
+system.cpu.iew.iewDispStoreInsts 5308956
+system.cpu.iew.iewDispNonSpecInsts 4394
+system.cpu.iew.iewIQFullEvents 183005
+system.cpu.iew.iewLSQFullEvents 362995
+system.cpu.iew.memOrderViolationEvents 1323
+system.cpu.iew.predictedTakenIncorrect 354101
+system.cpu.iew.predictedNotTakenIncorrect 451870
+system.cpu.iew.branchMispredicts 805971
+system.cpu.iew.iewExecutedInsts 100068536
+system.cpu.iew.iewExecLoadInsts 23799476
+system.cpu.iew.iewExecSquashedInsts 1185374
+system.cpu.iew.exec_swp 0
+system.cpu.iew.exec_nop 12823
+system.cpu.iew.exec_refs 28747002
+system.cpu.iew.exec_branches 20644390
+system.cpu.iew.exec_stores 4947526
+system.cpu.iew.exec_rate 0.854978
+system.cpu.iew.wb_sent 99653444
+system.cpu.iew.wb_count 99568306
+system.cpu.iew.wb_producers 59603520
+system.cpu.iew.wb_consumers 95472454
+system.cpu.iew.wb_rate 0.850705
+system.cpu.iew.wb_fanout 0.624301
+system.cpu.commit.commitSquashedInsts 17204380
+system.cpu.commit.commitNonSpecStalls 8218
+system.cpu.commit.branchMispredicts 780499
+system.cpu.commit.committed_per_cycle::samples 114317449
+system.cpu.commit.committed_per_cycle::mean 0.796498
+system.cpu.commit.committed_per_cycle::stdev 1.736161
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21%
+system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44%
+system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68%
+system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69%
+system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13%
+system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61%
+system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22%
+system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38%
+system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00%
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.commit.committed_per_cycle::min_value 0
+system.cpu.commit.committed_per_cycle::max_value 8
+system.cpu.commit.committed_per_cycle::total 114317449
+system.cpu.commit.committedInsts 90602408
+system.cpu.commit.committedOps 91053639
+system.cpu.commit.swp_count 0
+system.cpu.commit.refs 27220755
+system.cpu.commit.loads 22475911
+system.cpu.commit.membars 3888
+system.cpu.commit.branches 18732305
+system.cpu.commit.fp_insts 48
+system.cpu.commit.int_insts 72326352
+system.cpu.commit.function_calls 56148
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00%
+system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09%
+system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10%
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10%
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10%
+system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79%
+system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00%
+system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00%
+system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00%
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.commit.op_class_0::total 91053639
+system.cpu.commit.bw_lim_events 4142947
+system.cpu.rob.rob_reads 218426787
+system.cpu.rob.rob_writes 219173123
+system.cpu.timesIdled 593
+system.cpu.idleCycles 68291
+system.cpu.committedInsts 90589799
+system.cpu.committedOps 91041030
+system.cpu.cpi 1.292002
+system.cpu.cpi_total 1.292002
+system.cpu.ipc 0.773993
+system.cpu.ipc_total 0.773993
+system.cpu.int_regfile_reads 108095256
+system.cpu.int_regfile_writes 58597145
+system.cpu.fp_regfile_reads 58
+system.cpu.fp_regfile_writes 127
+system.cpu.cc_regfile_reads 368871207
+system.cpu.cc_regfile_writes 58517884
+system.cpu.misc_regfile_reads 28439348
+system.cpu.misc_regfile_writes 7784
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.tags.replacements 5470632
+system.cpu.dcache.tags.tagsinuse 511.768178
+system.cpu.dcache.tags.total_refs 18243100
+system.cpu.dcache.tags.sampled_refs 5471144
+system.cpu.dcache.tags.avg_refs 3.334421
+system.cpu.dcache.tags.warmup_cycle 38187500
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999547
+system.cpu.dcache.tags.occ_percent::total 0.999547
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 327
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 185
+system.cpu.dcache.tags.occ_task_id_percent::1024 1
+system.cpu.dcache.tags.tag_accesses 61896540
+system.cpu.dcache.tags.data_accesses 61896540
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.dcache.ReadReq_hits::cpu.data 13880582
+system.cpu.dcache.ReadReq_hits::total 13880582
+system.cpu.dcache.WriteReq_hits::cpu.data 4354214
+system.cpu.dcache.WriteReq_hits::total 4354214
+system.cpu.dcache.SoftPFReq_hits::cpu.data 522
+system.cpu.dcache.SoftPFReq_hits::total 522
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873
+system.cpu.dcache.LoadLockedReq_hits::total 3873
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887
+system.cpu.dcache.StoreCondReq_hits::total 3887
+system.cpu.dcache.demand_hits::cpu.data 18234796
+system.cpu.dcache.demand_hits::total 18234796
+system.cpu.dcache.overall_hits::cpu.data 18235318
+system.cpu.dcache.overall_hits::total 18235318
+system.cpu.dcache.ReadReq_misses::cpu.data 9588832
+system.cpu.dcache.ReadReq_misses::total 9588832
+system.cpu.dcache.WriteReq_misses::cpu.data 380767
+system.cpu.dcache.WriteReq_misses::total 380767
+system.cpu.dcache.SoftPFReq_misses::cpu.data 7
+system.cpu.dcache.SoftPFReq_misses::total 7
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 14
+system.cpu.dcache.LoadLockedReq_misses::total 14
+system.cpu.dcache.demand_misses::cpu.data 9969599
+system.cpu.dcache.demand_misses::total 9969599
+system.cpu.dcache.overall_misses::cpu.data 9969606
+system.cpu.dcache.overall_misses::total 9969606
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500
+system.cpu.dcache.ReadReq_miss_latency::total 89393317500
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083
+system.cpu.dcache.WriteReq_miss_latency::total 4103772083
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 302000
+system.cpu.dcache.demand_miss_latency::cpu.data 93497089583
+system.cpu.dcache.demand_miss_latency::total 93497089583
+system.cpu.dcache.overall_miss_latency::cpu.data 93497089583
+system.cpu.dcache.overall_miss_latency::total 93497089583
+system.cpu.dcache.ReadReq_accesses::cpu.data 23469414
+system.cpu.dcache.ReadReq_accesses::total 23469414
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981
+system.cpu.dcache.WriteReq_accesses::total 4734981
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 529
+system.cpu.dcache.SoftPFReq_accesses::total 529
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
+system.cpu.dcache.LoadLockedReq_accesses::total 3887
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887
+system.cpu.dcache.StoreCondReq_accesses::total 3887
+system.cpu.dcache.demand_accesses::cpu.data 28204395
+system.cpu.dcache.demand_accesses::total 28204395
+system.cpu.dcache.overall_accesses::cpu.data 28204924
+system.cpu.dcache.overall_accesses::total 28204924
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567
+system.cpu.dcache.ReadReq_miss_rate::total 0.408567
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416
+system.cpu.dcache.WriteReq_miss_rate::total 0.080416
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602
+system.cpu.dcache.demand_miss_rate::cpu.data 0.353477
+system.cpu.dcache.demand_miss_rate::total 0.353477
+system.cpu.dcache.overall_miss_rate::cpu.data 0.353470
+system.cpu.dcache.overall_miss_rate::total 0.353470
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255
+system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684
+system.cpu.dcache.demand_avg_miss_latency::total 9378.219684
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099
+system.cpu.dcache.overall_avg_miss_latency::total 9378.213099
+system.cpu.dcache.blocked_cycles::no_mshrs 331670
+system.cpu.dcache.blocked_cycles::no_targets 131340
+system.cpu.dcache.blocked::no_mshrs 121646
+system.cpu.dcache.blocked::no_targets 12838
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518
+system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566
+system.cpu.dcache.writebacks::writebacks 5470632
+system.cpu.dcache.writebacks::total 5470632
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269
+system.cpu.dcache.ReadReq_mshr_hits::total 4340269
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185
+system.cpu.dcache.WriteReq_mshr_hits::total 158185
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 14
+system.cpu.dcache.demand_mshr_hits::cpu.data 4498454
+system.cpu.dcache.demand_mshr_hits::total 4498454
+system.cpu.dcache.overall_mshr_hits::cpu.data 4498454
+system.cpu.dcache.overall_mshr_hits::total 4498454
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563
+system.cpu.dcache.ReadReq_mshr_misses::total 5248563
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582
+system.cpu.dcache.WriteReq_mshr_misses::total 222582
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4
+system.cpu.dcache.SoftPFReq_mshr_misses::total 4
+system.cpu.dcache.demand_mshr_misses::cpu.data 5471145
+system.cpu.dcache.demand_mshr_misses::total 5471145
+system.cpu.dcache.overall_mshr_misses::cpu.data 5471149
+system.cpu.dcache.overall_mshr_misses::total 5471149
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983
+system.cpu.dcache.demand_mshr_miss_latency::total 46120568983
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483
+system.cpu.dcache.overall_mshr_miss_latency::total 46120804483
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982
+system.cpu.dcache.demand_mshr_miss_rate::total 0.193982
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979
+system.cpu.dcache.overall_mshr_miss_rate::total 0.193979
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.tags.replacements 449
+system.cpu.icache.tags.tagsinuse 426.857560
+system.cpu.icache.tags.total_refs 32085580
+system.cpu.icache.tags.sampled_refs 907
+system.cpu.icache.tags.avg_refs 35375.501654
+system.cpu.icache.tags.warmup_cycle 0
+system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560
+system.cpu.icache.tags.occ_percent::cpu.inst 0.833706
+system.cpu.icache.tags.occ_percent::total 0.833706
+system.cpu.icache.tags.occ_task_id_blocks::1024 458
+system.cpu.icache.tags.age_task_id_blocks_1024::0 53
+system.cpu.icache.tags.age_task_id_blocks_1024::2 50
+system.cpu.icache.tags.age_task_id_blocks_1024::3 22
+system.cpu.icache.tags.age_task_id_blocks_1024::4 333
+system.cpu.icache.tags.occ_task_id_percent::1024 0.894531
+system.cpu.icache.tags.tag_accesses 64174375
+system.cpu.icache.tags.data_accesses 64174375
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.icache.ReadReq_hits::cpu.inst 32085580
+system.cpu.icache.ReadReq_hits::total 32085580
+system.cpu.icache.demand_hits::cpu.inst 32085580
+system.cpu.icache.demand_hits::total 32085580
+system.cpu.icache.overall_hits::cpu.inst 32085580
+system.cpu.icache.overall_hits::total 32085580
+system.cpu.icache.ReadReq_misses::cpu.inst 1154
+system.cpu.icache.ReadReq_misses::total 1154
+system.cpu.icache.demand_misses::cpu.inst 1154
+system.cpu.icache.demand_misses::total 1154
+system.cpu.icache.overall_misses::cpu.inst 1154
+system.cpu.icache.overall_misses::total 1154
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480
+system.cpu.icache.ReadReq_miss_latency::total 81624480
+system.cpu.icache.demand_miss_latency::cpu.inst 81624480
+system.cpu.icache.demand_miss_latency::total 81624480
+system.cpu.icache.overall_miss_latency::cpu.inst 81624480
+system.cpu.icache.overall_miss_latency::total 81624480
+system.cpu.icache.ReadReq_accesses::cpu.inst 32086734
+system.cpu.icache.ReadReq_accesses::total 32086734
+system.cpu.icache.demand_accesses::cpu.inst 32086734
+system.cpu.icache.demand_accesses::total 32086734
+system.cpu.icache.overall_accesses::cpu.inst 32086734
+system.cpu.icache.overall_accesses::total 32086734
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036
+system.cpu.icache.ReadReq_miss_rate::total 0.000036
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000036
+system.cpu.icache.demand_miss_rate::total 0.000036
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000036
+system.cpu.icache.overall_miss_rate::total 0.000036
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.demand_avg_miss_latency::total 70731.785095
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095
+system.cpu.icache.overall_avg_miss_latency::total 70731.785095
+system.cpu.icache.blocked_cycles::no_mshrs 21770
+system.cpu.icache.blocked_cycles::no_targets 1853
+system.cpu.icache.blocked::no_mshrs 229
+system.cpu.icache.blocked::no_targets 7
+system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502
+system.cpu.icache.avg_blocked_cycles::no_targets 264.714286
+system.cpu.icache.writebacks::writebacks 449
+system.cpu.icache.writebacks::total 449
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246
+system.cpu.icache.ReadReq_mshr_hits::total 246
+system.cpu.icache.demand_mshr_hits::cpu.inst 246
+system.cpu.icache.demand_mshr_hits::total 246
+system.cpu.icache.overall_mshr_hits::cpu.inst 246
+system.cpu.icache.overall_mshr_hits::total 246
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908
+system.cpu.icache.ReadReq_mshr_misses::total 908
+system.cpu.icache.demand_mshr_misses::cpu.inst 908
+system.cpu.icache.demand_mshr_misses::total 908
+system.cpu.icache.overall_mshr_misses::cpu.inst 908
+system.cpu.icache.overall_mshr_misses::total 908
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.demand_mshr_miss_latency::total 61609984
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984
+system.cpu.icache.overall_mshr_miss_latency::total 61609984
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.demand_mshr_miss_rate::total 0.000028
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028
+system.cpu.icache.overall_mshr_miss_rate::total 0.000028
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667
+system.cpu.l2cache.prefetcher.pfIdentified 5295978
+system.cpu.l2cache.prefetcher.pfBufferHit 268023
+system.cpu.l2cache.prefetcher.pfInCache 0
+system.cpu.l2cache.prefetcher.pfRemovedFull 0
+system.cpu.l2cache.prefetcher.pfSpanPage 14076270
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.tags.replacements 99
+system.cpu.l2cache.tags.tagsinuse 11218.637670
+system.cpu.l2cache.tags.total_refs 5292117
+system.cpu.l2cache.tags.sampled_refs 14656
+system.cpu.l2cache.tags.avg_refs 361.088769
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012
+system.cpu.l2cache.tags.occ_percent::writebacks 0.680659
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072
+system.cpu.l2cache.tags.occ_percent::total 0.684731
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 67
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399
+system.cpu.l2cache.tags.tag_accesses 180525307
+system.cpu.l2cache.tags.data_accesses 180525307
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_hits::total 5460197
+system.cpu.l2cache.WritebackClean_hits::writebacks 7956
+system.cpu.l2cache.WritebackClean_hits::total 7956
+system.cpu.l2cache.ReadExReq_hits::cpu.data 225753
+system.cpu.l2cache.ReadExReq_hits::total 225753
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207
+system.cpu.l2cache.ReadCleanReq_hits::total 207
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769
+system.cpu.l2cache.ReadSharedReq_hits::total 5241769
+system.cpu.l2cache.demand_hits::cpu.inst 207
+system.cpu.l2cache.demand_hits::cpu.data 5467522
+system.cpu.l2cache.demand_hits::total 5467729
+system.cpu.l2cache.overall_hits::cpu.inst 207
+system.cpu.l2cache.overall_hits::cpu.data 5467522
+system.cpu.l2cache.overall_hits::total 5467729
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_misses::total 5
+system.cpu.l2cache.ReadExReq_misses::cpu.data 499
+system.cpu.l2cache.ReadExReq_misses::total 499
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701
+system.cpu.l2cache.ReadCleanReq_misses::total 701
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123
+system.cpu.l2cache.ReadSharedReq_misses::total 3123
+system.cpu.l2cache.demand_misses::cpu.inst 701
+system.cpu.l2cache.demand_misses::cpu.data 3622
+system.cpu.l2cache.demand_misses::total 4323
+system.cpu.l2cache.overall_misses::cpu.inst 701
+system.cpu.l2cache.overall_misses::cpu.data 3622
+system.cpu.l2cache.overall_misses::total 4323
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500
+system.cpu.l2cache.UpgradeReq_miss_latency::total 105500
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000
+system.cpu.l2cache.ReadExReq_miss_latency::total 66196000
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.demand_miss_latency::cpu.data 683496000
+system.cpu.l2cache.demand_miss_latency::total 742803500
+system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500
+system.cpu.l2cache.overall_miss_latency::cpu.data 683496000
+system.cpu.l2cache.overall_miss_latency::total 742803500
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197
+system.cpu.l2cache.WritebackDirty_accesses::total 5460197
+system.cpu.l2cache.WritebackClean_accesses::writebacks 7956
+system.cpu.l2cache.WritebackClean_accesses::total 7956
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_accesses::total 5
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252
+system.cpu.l2cache.ReadExReq_accesses::total 226252
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908
+system.cpu.l2cache.ReadCleanReq_accesses::total 908
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892
+system.cpu.l2cache.ReadSharedReq_accesses::total 5244892
+system.cpu.l2cache.demand_accesses::cpu.inst 908
+system.cpu.l2cache.demand_accesses::cpu.data 5471144
+system.cpu.l2cache.demand_accesses::total 5472052
+system.cpu.l2cache.overall_accesses::cpu.inst 908
+system.cpu.l2cache.overall_accesses::cpu.data 5471144
+system.cpu.l2cache.overall_accesses::total 5472052
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.demand_miss_rate::total 0.000790
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662
+system.cpu.l2cache.overall_miss_rate::total 0.000790
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828
+system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.unused_prefetches 1
+system.cpu.l2cache.writebacks::writebacks 74
+system.cpu.l2cache.writebacks::total 74
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158
+system.cpu.l2cache.ReadExReq_mshr_hits::total 158
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1
+system.cpu.l2cache.demand_mshr_hits::cpu.data 180
+system.cpu.l2cache.demand_mshr_hits::total 181
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1
+system.cpu.l2cache.overall_mshr_hits::cpu.data 180
+system.cpu.l2cache.overall_mshr_hits::total 181
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.HardPFReq_mshr_misses::total 316332
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 5
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341
+system.cpu.l2cache.ReadExReq_mshr_misses::total 341
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 700
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3442
+system.cpu.l2cache.demand_mshr_misses::total 4142
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 700
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3442
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332
+system.cpu.l2cache.overall_mshr_misses::total 320474
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.demand_mshr_miss_latency::total 692500000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507
+system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441
+system.cpu.toL2Bus.snoop_filter.tot_requests 10943138
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928
+system.cpu.toL2Bus.snoop_filter.tot_snoops 301927
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.cpu.toL2Bus.trans_dist::ReadResp 5245799
+system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271
+system.cpu.toL2Bus.trans_dist::WritebackClean 10884
+system.cpu.toL2Bus.trans_dist::CleanEvict 25
+system.cpu.toL2Bus.trans_dist::HardPFReq 318221
+system.cpu.toL2Bus.trans_dist::HardPFResp 6
+system.cpu.toL2Bus.trans_dist::UpgradeReq 5
+system.cpu.toL2Bus.trans_dist::UpgradeResp 5
+system.cpu.toL2Bus.trans_dist::ReadExReq 226252
+system.cpu.toL2Bus.trans_dist::ReadExResp 226252
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 908
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936
+system.cpu.toL2Bus.pkt_count::total 16415200
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048
+system.cpu.toL2Bus.pkt_size::total 700360832
+system.cpu.toL2Bus.snoops 318326
+system.cpu.toL2Bus.snoopTraffic 5120
+system.cpu.toL2Bus.snoop_fanout::samples 5790377
+system.cpu.toL2Bus.snoop_fanout::mean 0.052651
+system.cpu.toL2Bus.snoop_fanout::stdev 0.223337
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73%
+system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 5790377
+system.cpu.toL2Bus.reqLayer0.occupancy 10942650026
+system.cpu.toL2Bus.reqLayer0.utilization 18.7
+system.cpu.toL2Bus.snoopLayer0.occupancy 9032
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 1362995
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 8206721993
+system.cpu.toL2Bus.respLayer1.utilization 14.0
+system.membus.snoop_filter.tot_requests 18651
+system.membus.snoop_filter.hit_single_requests 3037
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.membus.trans_dist::ReadResp 18205
+system.membus.trans_dist::WritebackDirty 74
+system.membus.trans_dist::CleanEvict 25
+system.membus.trans_dist::UpgradeReq 6
+system.membus.trans_dist::ReadExReq 340
+system.membus.trans_dist::ReadExResp 340
+system.membus.trans_dist::ReadSharedReq 18206
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196
+system.membus.pkt_count::total 37196
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616
+system.membus.pkt_size::total 1191616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 18552
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 18552
+system.membus.reqLayer0.occupancy 29380556
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------