---------- Begin Simulation Statistics ----------
-sim_seconds 0.026909 # Number of seconds simulated
-sim_ticks 26909234500 # Number of ticks simulated
-final_tick 26909234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 142304 # Simulator instruction rate (inst/s)
-host_op_rate 143325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42270537 # Simulator tick rate (ticks/s)
-host_mem_usage 446544 # Number of bytes of host memory used
-host_seconds 636.60 # Real time elapsed on the host
-sim_insts 90589798 # Number of instructions simulated
-sim_ops 91240351 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1671991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35216461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 36888452 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1671991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1671991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1671991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35216461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 36888452 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15510 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 987 # Per bank write bursts
-system.physmem.perBankRdBursts::1 885 # Per bank write bursts
-system.physmem.perBankRdBursts::2 942 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1049 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1078 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 957 # Per bank write bursts
-system.physmem.perBankRdBursts::10 935 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 905 # Per bank write bursts
-system.physmem.perBankRdBursts::13 865 # Per bank write bursts
-system.physmem.perBankRdBursts::14 877 # Per bank write bursts
-system.physmem.perBankRdBursts::15 896 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 26909036500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 15510 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 10635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1363 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 726.491563 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 533.334896 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 387.223532 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 140 10.27% 10.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 158 11.59% 21.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 56 4.11% 25.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 68 4.99% 30.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 57 4.18% 35.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 39 2.86% 38.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 24 1.76% 39.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 39 2.86% 42.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 782 57.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1363 # Bytes accessed per row activation
-system.physmem.totQLat 83369750 # Total ticks spent queuing
-system.physmem.totMemAccLat 374182250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5375.23 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24125.23 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 36.89 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 36.89 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.29 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 14137 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1734947.55 # Average gap between requests
-system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 24303660500 # Time in different power states
-system.physmem.memoryStateTime::REF 898300000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1704463000 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 36888452 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 972 # Transaction distribution
-system.membus.trans_dist::ReadResp 972 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31026 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 31026 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 992640 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 19094500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 145899997 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 26684247 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22003797 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 841589 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11372801 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11278925 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.174557 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 69990 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions.
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53818470 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14166768 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127874482 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26684247 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11348915 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24030832 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4761225 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11326508 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13838942 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329737 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53427318 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.409937 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.214887 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29434889 55.09% 55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3387974 6.34% 61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2027945 3.80% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1552978 2.91% 68.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1665988 3.12% 71.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918810 5.46% 76.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1512193 2.83% 79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1089826 2.04% 81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9836715 18.41% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53427318 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.495820 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.376033 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16930628 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9172800 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22402161 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1027234 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3894495 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4441775 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8644 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126055074 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42561 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3894495 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18710503 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3595532 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 186271 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21547494 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5493023 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123139917 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 426575 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4604902 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1527 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143588109 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536432016 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 499923969 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 641 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36173923 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4624 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4622 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12547663 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29472846 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5519091 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2169224 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1269381 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118159243 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8489 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105145248 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 78272 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26728441 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65602174 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 271 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53427318 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.968005 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.908888 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15370604 28.77% 28.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11662585 21.83% 50.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8230563 15.41% 66.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6832993 12.79% 78.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4979120 9.32% 88.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2926966 5.48% 93.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2444206 4.57% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 536236 1.00% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 444045 0.83% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53427318 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 46059 6.94% 6.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 26 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 341162 51.43% 58.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 276052 41.62% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74418244 70.78% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 122 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 157 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25603497 24.35% 95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5112252 4.86% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105145248 # Type of FU issued
-system.cpu.iq.rate 1.953702 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 663299 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006308 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264458762 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144900942 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102674293 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 623 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 845 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 263 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105808235 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 312 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 440410 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6898880 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6071 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6331 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 774247 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31563 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3894495 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 960394 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127228 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118180427 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309851 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29472846 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5519091 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4601 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 65954 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6808 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6331 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446096 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445462 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891558 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104169534 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25284727 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 975714 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12695 # number of nop insts executed
-system.cpu.iew.exec_refs 30339844 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21324580 # Number of branches executed
-system.cpu.iew.exec_stores 5055117 # Number of stores executed
-system.cpu.iew.exec_rate 1.935572 # Inst execution rate
-system.cpu.iew.wb_sent 102952816 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102674556 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62244775 # num instructions producing a value
-system.cpu.iew.wb_consumers 104288684 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.907794 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596851 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26930418 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833018 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49532823 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.842273 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541112 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 20056290 40.49% 40.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13134081 26.52% 67.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4165062 8.41% 75.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3431851 6.93% 82.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1531687 3.09% 85.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 719294 1.45% 86.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 966848 1.95% 88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 252784 0.51% 89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5274926 10.65% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49532823 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90602407 # Number of instructions committed
-system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27318810 # Number of memory references committed
-system.cpu.commit.loads 22573966 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18732304 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction
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-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction
-system.cpu.commit.bw_lim_events 5274926 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162435541 # The number of ROB reads
-system.cpu.rob.rob_writes 240280947 # The number of ROB writes
-system.cpu.timesIdled 46113 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 391152 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90589798 # Number of Instructions Simulated
-system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.594090 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.594090 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.683247 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.683247 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495503749 # number of integer regfile reads
-system.cpu.int_regfile_writes 120538753 # number of integer regfile writes
-system.cpu.fp_regfile_reads 136 # number of floating regfile reads
-system.cpu.fp_regfile_writes 324 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29202777 # number of misc regfile reads
-system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 4498112646 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 904542 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 904541 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 942913 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 43808 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 43808 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1459 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838157 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2839616 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120993984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 121040512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 121040512 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 1888546500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1214249 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1424437743 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
-system.cpu.icache.tags.replacements 4 # number of replacements
-system.cpu.icache.tags.tagsinuse 629.782020 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 13837957 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 727 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 19034.328748 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 629.782020 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.307511 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.307511 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 723 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 671 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.353027 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 27678613 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 27678613 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 13837957 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13837957 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13837957 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13837957 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13837957 # number of overall hits
-system.cpu.icache.overall_hits::total 13837957 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses
-system.cpu.icache.overall_misses::total 984 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 66510498 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 66510498 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 66510498 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 66510498 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 66510498 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 66510498 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13838941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13838941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13838941 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13838941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13838941 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13838941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67591.969512 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67591.969512 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67591.969512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67591.969512 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67591.969512 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 649 # number of cycles access was blocked
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-system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
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-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 252 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 252 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 252 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 252 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 50737500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 50737500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50737500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 50737500 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69313.524590 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69313.524590 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69313.524590 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69313.524590 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 10725.417134 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 1831324 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 15493 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 118.203318 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 9880.636903 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 615.219172 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13611 # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses 15189406 # Number of tag accesses
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-system.cpu.l2cache.ReadReq_hits::cpu.data 903531 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 903555 # number of ReadReq hits
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-system.cpu.l2cache.Writeback_hits::total 942913 # number of Writeback hits
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-system.cpu.l2cache.ReadExReq_hits::total 29270 # number of ReadExReq hits
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-system.cpu.l2cache.overall_hits::cpu.data 932801 # number of overall hits
-system.cpu.l2cache.overall_hits::total 932825 # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
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-system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76581.541219 # average ReadReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66879.350667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66879.350667 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70692.826705 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67062.040224 # average overall miss latency
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-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 5790377
+system.cpu.toL2Bus.reqLayer0.occupancy 10942650026
+system.cpu.toL2Bus.reqLayer0.utilization 18.7
+system.cpu.toL2Bus.snoopLayer0.occupancy 9032
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 1362995
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 8206721993
+system.cpu.toL2Bus.respLayer1.utilization 14.0
+system.membus.snoop_filter.tot_requests 18651
+system.membus.snoop_filter.hit_single_requests 3037
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000
+system.membus.trans_dist::ReadResp 18205
+system.membus.trans_dist::WritebackDirty 74
+system.membus.trans_dist::CleanEvict 25
+system.membus.trans_dist::UpgradeReq 6
+system.membus.trans_dist::ReadExReq 340
+system.membus.trans_dist::ReadExResp 340
+system.membus.trans_dist::ReadSharedReq 18206
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196
+system.membus.pkt_count::total 37196
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616
+system.membus.pkt_size::total 1191616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 18552
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 18552
+system.membus.reqLayer0.occupancy 29380556
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff