---------- Begin Simulation Statistics ----------
-sim_seconds 0.026786 # Number of seconds simulated
-sim_ticks 26786364500 # Number of ticks simulated
-final_tick 26786364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184396 # Simulator instruction rate (inst/s)
-host_op_rate 185720 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54518089 # Simulator tick rate (ticks/s)
-host_mem_usage 410024 # Number of bytes of host memory used
-host_seconds 491.33 # Real time elapsed on the host
-sim_insts 90599358 # Number of instructions simulated
-sim_ops 91249911 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992768 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15512 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1689218 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35373221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37062439 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1689218 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1689218 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1689218 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35373221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37062439 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15512 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15514 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 992768 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 992768 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1014 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 997 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 941 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1012 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 978 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26786185500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15512 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 0 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 10748 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 45050979 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 279102979 # Sum of mem lat for all requests
-system.physmem.totBusLat 62048000 # Total cycles spent in databus access
-system.physmem.totBankLat 172004000 # Total cycles spent in bank access
-system.physmem.avgQLat 2904.27 # Average queueing delay per request
-system.physmem.avgBankLat 11088.45 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 17992.71 # Average memory access latency
-system.physmem.avgRdBW 37.06 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 37.06 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.23 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 15087 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1726804.12 # Average gap between requests
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53572730 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26681190 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22001511 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 842165 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11371976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11281654 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 70159 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14169802 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127871795 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26681190 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11351813 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24032420 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4759415 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11256916 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13841949 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 329938 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53360207 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.412919 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.215578 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29366337 55.03% 55.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3387610 6.35% 61.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2027655 3.80% 65.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1555895 2.92% 68.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1666559 3.12% 71.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2918525 5.47% 76.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1512890 2.84% 79.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1090822 2.04% 81.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9833914 18.43% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53360207 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498037 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.386882 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16933273 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9104448 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22449831 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 980264 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3892391 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4441470 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126048465 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42747 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3892391 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18713903 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3544404 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 187474 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21547168 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5474867 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123140443 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 417251 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4594278 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1244 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143600920 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536395589 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536390601 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4988 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36171438 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6558 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6556 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12502916 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29470902 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5524793 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2121904 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1282766 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118150173 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 10438 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105160593 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 79722 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26714603 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65515716 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 308 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53360207 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.970768 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.910908 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15336122 28.74% 28.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11634873 21.80% 50.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8272987 15.50% 66.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6735590 12.62% 78.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4978396 9.33% 88.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2962958 5.55% 93.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2475458 4.64% 98.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 518730 0.97% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 445093 0.83% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53360207 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 45281 6.85% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340422 51.49% 58.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 275350 41.65% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74420683 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10977 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 148 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 190 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25610261 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5118329 4.87% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105160593 # Type of FU issued
-system.cpu.iq.rate 1.962950 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 661080 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006286 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264421445 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144879638 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102686211 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 750 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1049 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 331 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105821300 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 373 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 443954 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6895024 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7123 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6272 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 778037 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31249 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3892391 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 925499 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 127080 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118173306 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309093 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29470902 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5524793 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6532 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66339 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6977 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6272 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446356 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445453 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 891809 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104181304 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25288567 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 979289 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12695 # number of nop insts executed
-system.cpu.iew.exec_refs 30349931 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21325057 # Number of branches executed
-system.cpu.iew.exec_stores 5061364 # Number of stores executed
-system.cpu.iew.exec_rate 1.944670 # Inst execution rate
-system.cpu.iew.wb_sent 102965645 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102686542 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62242061 # num instructions producing a value
-system.cpu.iew.wb_consumers 104289210 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.916769 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596822 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26913567 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 833602 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49467817 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.844887 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541636 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19986876 40.40% 40.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13133000 26.55% 66.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4163273 8.42% 75.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3434953 6.94% 82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1533681 3.10% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 739386 1.49% 86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 948988 1.92% 88.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 248747 0.50% 89.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5278913 10.67% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49467817 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90611967 # Number of instructions committed
-system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27322634 # Number of memory references committed
-system.cpu.commit.loads 22575878 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18734216 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72533322 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5278913 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162359257 # The number of ROB reads
-system.cpu.rob.rob_writes 240263976 # The number of ROB writes
-system.cpu.timesIdled 43500 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 212523 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90599358 # Number of Instructions Simulated
-system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated
-system.cpu.cpi 0.591315 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.591315 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.691147 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.691147 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495578845 # number of integer regfile reads
-system.cpu.int_regfile_writes 120555497 # number of integer regfile writes
-system.cpu.fp_regfile_reads 176 # number of floating regfile reads
-system.cpu.fp_regfile_writes 427 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29099412 # number of misc regfile reads
-system.cpu.misc_regfile_writes 11608 # number of misc regfile writes
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 632.599736 # Cycle average of tags in use
-system.cpu.icache.total_refs 13840965 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 735 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 18831.244898 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 632.599736 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.308887 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.308887 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13840965 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13840965 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13840965 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13840965 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13840965 # number of overall hits
-system.cpu.icache.overall_hits::total 13840965 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 983 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 983 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 983 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 983 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 983 # number of overall misses
-system.cpu.icache.overall_misses::total 983 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 48291499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 48291499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 48291499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 48291499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 48291499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 48291499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 13841948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 13841948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 13841948 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 13841948 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 13841948 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 13841948 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49126.652085 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49126.652085 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49126.652085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49126.652085 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49126.652085 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1099 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 122.111111 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36763999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 36763999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36763999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 36763999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36763999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36763999 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49748.307172 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49748.307172 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49748.307172 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49748.307172 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 943495 # number of replacements
-system.cpu.dcache.tagsinuse 3673.924289 # Cycle average of tags in use
-system.cpu.dcache.total_refs 28145440 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 947591 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 29.702097 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7941416000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3673.924289 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.896954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.896954 # Average percentage of cache occupancy
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-system.cpu.dcache.demand_avg_miss_latency::total 14043.038113 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14043.038113 # average overall miss latency
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334084 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334084 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.016357 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961905 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015624 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.016357 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37933.640736 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40387.187266 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38606.224846 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28944.857752 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28944.857752 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37933.640736 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29151.213847 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29551.495939 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.membus.snoops 0
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+system.membus.snoop_fanout::mean 0
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+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
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+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff