stats: x86: update stats missed out on in preivous changeset

[gem5.git] / tests / long / se / 10.mcf / ref / x86 / linux / o3-timing / config.ini

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index a7b21f16f5c3d7d832cde90f8eb54fa6d91fc0d7..399eedecee2a0146902ffa69aa01dcea93f9cd95 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -10,17 +10,20 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -36,7 +39,9 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -70,6 +75,7 @@ do_statistics_insts=true
 dtb=system.cpu.dtb
 eventq_index=0
 fetchBufferSize=64
+fetchQueueSize=32
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -115,13 +121,13 @@ smtLSQThreshold=100
 smtNumFetchingThreads=1
 smtROBPolicy=Partitioned
 smtROBThreshold=100
+socket_id=0
 squashWidth=8
 store_set_clear_period=250000
 switched_out=false
 system=system
 tracer=system.cpu.tracer
 trapLatency=13
-wbDepth=1
 wbWidth=8
 workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
@@ -134,7 +140,7 @@ clk_domain=system.cpu_clk_domain
 eventq_index=0
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -148,7 +154,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -156,20 +161,21 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -181,6 +187,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -214,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -228,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
-opLat=20
+opLat=1
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -249,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -277,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -305,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -319,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -466,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -480,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -501,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -511,20 +518,21 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -536,6 +544,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -575,20 +584,21 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -600,13 +610,18 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -621,14 +636,16 @@ eventq_index=0
 type=LiveProcess
 cmd=mcf mcf.in
 cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+drivers=
 egid=100
 env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -636,28 +653,68 @@ ppid=99
 simpoint=55300000000
 system=system
 uid=100
+useArchPT=false
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.voltage_domain
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -665,30 +722,45 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:268435455
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
+tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[0]
 
 [system.voltage_domain]