---------- Begin Simulation Statistics ----------
-sim_seconds 0.370011 # Number of seconds simulated
-sim_ticks 370010840000 # Number of ticks simulated
-final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.365989 # Number of seconds simulated
+sim_ticks 365989065000 # Number of ticks simulated
+final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 912216 # Simulator instruction rate (inst/s)
-host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2136418129 # Simulator tick rate (ticks/s)
-host_mem_usage 353708 # Number of bytes of host memory used
-host_seconds 173.19 # Real time elapsed on the host
-sim_insts 157988583 # Number of instructions simulated
-sim_ops 278192520 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 4900800 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 1885440 # Number of bytes written to this memory
-system.physmem.num_reads 76575 # Number of read requests responded to by this memory
-system.physmem.num_writes 29460 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 466388 # Simulator instruction rate (inst/s)
+host_op_rate 821234 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1080412484 # Simulator tick rate (ticks/s)
+host_mem_usage 431468 # Number of bytes of host memory used
+host_seconds 338.75 # Real time elapsed on the host
+sim_insts 157988548 # Number of instructions simulated
+sim_ops 278192465 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 740021680 # number of cpu cycles simulated
+system.cpu.numCycles 731978130 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 157988583 # Number of instructions committed
-system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
+system.cpu.committedInsts 157988548 # Number of instructions committed
+system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186228 # number of integer instructions
+system.cpu.num_func_calls 8475189 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
+system.cpu.num_int_insts 278186175 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
-system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
+system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read
+system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_mem_refs 122219139 # number of memory refs
-system.cpu.num_load_insts 90779388 # Number of load instructions
-system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_mem_refs 122219137 # number of memory refs
+system.cpu.num_load_insts 90779385 # Number of load instructions
+system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 740021680 # Number of busy cycles
+system.cpu.num_busy_cycles 731978130 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
-system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 665.632508 # Cycle average of tags in use
+system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 217695401 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
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+system.cpu.icache.overall_hits::total 217695357 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
-system.cpu.l2cache.writebacks::total 29460 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff