stats: update stats for ARMv8 changes

[gem5.git] / tests / long / se / 20.parser / ref / arm / linux / simple-atomic / config.ini

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 7b35bd3ad57bf26e641a84edf96dc15aaebf3ea2..b14a667a9ed0d37364369a1aa1822a7032364aac 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,9 +14,11 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
@@ -33,23 +37,27 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
+children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -72,54 +80,124 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[6]
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
 id_isar3=17899825
 id_isar4=268501314
 id_isar5=0
-id_mmfr0=3
+id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
-id_mmfr3=4027589137
+id_mmfr3=34611729
 id_pfr0=49
-id_pfr1=1
-midr=890224640
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,9 +207,10 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,23 +222,26 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +251,6 @@ port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000