---------- Begin Simulation Statistics ----------
-sim_seconds 0.451526 # Number of seconds simulated
-sim_ticks 451526391500 # Number of ticks simulated
-final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.481958 # Number of seconds simulated
+sim_ticks 481957625500 # Number of ticks simulated
+final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97078 # Simulator instruction rate (inst/s)
-host_op_rate 179507 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53010367 # Simulator tick rate (ticks/s)
-host_mem_usage 427448 # Number of bytes of host memory used
-host_seconds 8517.70 # Real time elapsed on the host
-sim_insts 826877109 # Number of instructions simulated
-sim_ops 1528988701 # Number of ops (including micro ops) simulated
+host_inst_rate 104668 # Simulator instruction rate (inst/s)
+host_op_rate 193689 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61009723 # Simulator tick rate (ticks/s)
+host_mem_usage 318640 # Number of bytes of host memory used
+host_seconds 7899.69 # Real time elapsed on the host
+sim_insts 826847303 # Number of instructions simulated
+sim_ops 1530082520 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386877 # Number of read requests accepted
-system.physmem.writeReqs 294030 # Number of write requests accepted
-system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386855 # Number of read requests accepted
+system.physmem.writeReqs 294920 # Number of write requests accepted
+system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24137 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26529 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24699 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24593 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23302 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23749 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24449 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24297 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23610 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23919 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24516 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26460 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24685 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24442 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23203 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23588 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24636 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24397 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23786 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23509 # Per bank write bursts
system.physmem.perBankRdBursts::10 24817 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24050 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23346 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22971 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24088 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23983 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18558 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19844 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18955 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18948 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18446 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18985 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18975 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18547 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18155 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18842 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17721 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16974 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17821 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17824 # Per bank write bursts
+system.physmem.perBankRdBursts::11 23975 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23290 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22963 # Per bank write bursts
+system.physmem.perBankRdBursts::14 23965 # Per bank write bursts
+system.physmem.perBankRdBursts::15 24296 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18881 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19925 # Per bank write bursts
+system.physmem.perBankWrBursts::2 19022 # Per bank write bursts
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+system.physmem.perBankWrBursts::6 19142 # Per bank write bursts
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+system.physmem.perBankWrBursts::8 18675 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17903 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18899 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17761 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17398 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 17797 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17948 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 451526286000 # Total gap between requests
+system.physmem.totGap 481957508500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386877 # Read request sizes (log2)
+system.physmem.readPktSize::6 386855 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 294030 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294920 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads
-system.physmem.totQLat 4244351250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads
+system.physmem.totQLat 4249579000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.75 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes
+system.physmem.busUtil 0.71 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing
-system.physmem.readRowHits 317756 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215101 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes
-system.physmem.avgGap 663124.75 # Average gap between requests
-system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ)
-system.physmem_0.averagePower 690.421834 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states
+system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing
+system.physmem.readRowHits 315674 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215465 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes
+system.physmem.avgGap 706915.78 # Average gap between requests
+system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ)
+system.physmem_0.averagePower 690.294629 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ)
-system.physmem_1.averagePower 689.421031 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states
+system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ)
+system.physmem_1.averagePower 689.434954 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 231910847 # Number of BP lookups
-system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits
+system.cpu.branchPred.lookups 297786504 # Number of BP lookups
+system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 0 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 903052797 # number of cpu cycles simulated
+system.cpu.numCycles 963915252 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 921 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued
-system.cpu.iq.rate 2.025311 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued
+system.cpu.iq.rate 2.074089 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed
-system.cpu.iew.exec_branches 171967250 # Number of branches executed
-system.cpu.iew.exec_stores 170119293 # Number of stores executed
-system.cpu.iew.exec_rate 2.001969 # Inst execution rate
-system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1369352269 # num instructions producing a value
-system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed
+system.cpu.iew.exec_branches 185171662 # Number of branches executed
+system.cpu.iew.exec_stores 178831439 # Number of stores executed
+system.cpu.iew.exec_rate 2.018648 # Inst execution rate
+system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1457092334 # num instructions producing a value
+system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 826877109 # Number of instructions committed
-system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 826847303 # Number of instructions committed
+system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 533262343 # Number of memory references committed
-system.cpu.commit.loads 384102157 # Number of loads committed
+system.cpu.commit.refs 533241508 # Number of memory references committed
+system.cpu.commit.loads 384083313 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 149758583 # Number of branches committed
+system.cpu.commit.branches 149981740 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions.
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2859299655 # The number of ROB reads
-system.cpu.rob.rob_writes 4304507020 # The number of ROB writes
-system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 826877109 # Number of Instructions Simulated
-system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads
-system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6855 # number of floating regfile reads
-system.cpu.fp_regfile_writes 205 # number of floating regfile writes
-system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads
-system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes
-system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads
+system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction
+system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 3177371770 # The number of ROB reads
+system.cpu.rob.rob_writes 4973814894 # The number of ROB writes
+system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 826847303 # Number of Instructions Simulated
+system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads
+system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes
+system.cpu.fp_regfile_reads 239177 # number of floating regfile reads
+system.cpu.fp_regfile_writes 8 # number of floating regfile writes
+system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads
+system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes
+system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2534340 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 2545945 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits
-system.cpu.dcache.overall_hits::total 388309263 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses
-system.cpu.dcache.overall_misses::total 3694697 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits
+system.cpu.dcache.overall_hits::total 421064470 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 179848 # Transaction distribution
-system.membus.trans_dist::ReadResp 179848 # Transaction distribution
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+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 861081 # Request fanout histogram
+system.membus.snoop_fanout::samples 740563 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 861081 # Request fanout histogram
-system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.membus.snoop_fanout::total 740563 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff