---------- Begin Simulation Statistics ----------
-sim_seconds 0.434496 # Number of seconds simulated
-sim_ticks 434496110500 # Number of ticks simulated
-final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.451764 # Number of seconds simulated
+sim_ticks 451764406000 # Number of ticks simulated
+final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78440 # Simulator instruction rate (inst/s)
-host_op_rate 145045 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41217689 # Simulator tick rate (ticks/s)
-host_mem_usage 343084 # Number of bytes of host memory used
-host_seconds 10541.50 # Real time elapsed on the host
+host_inst_rate 99375 # Simulator instruction rate (inst/s)
+host_op_rate 183755 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54293474 # Simulator tick rate (ticks/s)
+host_mem_usage 421524 # Number of bytes of host memory used
+host_seconds 8320.79 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
-sim_ops 1528988699 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385622 # Total number of read requests seen
-system.physmem.writeReqs 293652 # Total number of write requests seen
-system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 24679680 # Total number of bytes read from memory
-system.physmem.bytesWritten 18793728 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 434496092500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 385622 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 0 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 293652 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+sim_ops 1528988701 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386948 # Number of read requests accepted
+system.physmem.writeReqs 294074 # Number of write requests accepted
+system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24122 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26505 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24681 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24611 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23302 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23732 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24448 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24311 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23620 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23937 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24812 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24076 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23393 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22985 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24096 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23981 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18558 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19850 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18948 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18946 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18437 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18993 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18991 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18543 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18160 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18841 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17736 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17380 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16967 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17832 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17826 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 451764392500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 386948 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 294074 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests
-system.physmem.totBusLat 1541944000 # Total cycles spent in databus access
-system.physmem.totBankLat 6529040000 # Total cycles spent in bank access
-system.physmem.avgQLat 9056.08 # Average queueing delay per request
-system.physmem.avgBankLat 16937.17 # Average bank access latency per request
-system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29993.24 # Average memory access latency
-system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.63 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 9.57 # Average write queue length over time
-system.physmem.readRowHits 340592 # Number of row buffer hits during reads
-system.physmem.writeRowHits 151278 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes
-system.physmem.avgGap 639647.76 # Average gap between requests
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads
+system.physmem.totQLat 4338654000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.75 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 317693 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215552 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes
+system.physmem.avgGap 663362.41 # Average gap between requests
+system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states
+system.physmem.memoryStateTime::REF 15085200000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.membus.trans_dist::ReadReq 179971 # Transaction distribution
+system.membus.trans_dist::ReadResp 179970 # Transaction distribution
+system.membus.trans_dist::Writeback 294074 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206977 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206977 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 860082 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 860082 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 231811700 # Number of BP lookups
+system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 868992222 # number of cpu cycles simulated
+system.cpu.numCycles 903528833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued
-system.cpu.iq.rate 2.080881 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued
+system.cpu.iq.rate 2.024408 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed
-system.cpu.iew.exec_branches 169281204 # Number of branches executed
-system.cpu.iew.exec_stores 170685262 # Number of stores executed
-system.cpu.iew.exec_rate 2.049012 # Inst execution rate
-system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1341657182 # num instructions producing a value
-system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value
+system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171944433 # Number of branches executed
+system.cpu.iew.exec_stores 170144104 # Number of stores executed
+system.cpu.iew.exec_rate 2.001031 # Inst execution rate
+system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1369602342 # num instructions producing a value
+system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 826877109 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 149758583 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions.
-system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2749615680 # The number of ROB reads
-system.cpu.rob.rob_writes 4138789024 # The number of ROB writes
-system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2860250697 # The number of ROB reads
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+system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
-system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
-system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads
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+system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram
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+system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_hits::total 2325 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 219204 # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total 219204 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 219204 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 865886999 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 865886999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865886999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 865886999 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001263 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.001263 # mshr miss rate for demand accesses
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-system.cpu.dcache.ReadReq_mshr_hits::total 1126114 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16846 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16846 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1142960 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1142960 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1142960 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff