---------- Begin Simulation Statistics ----------
-sim_seconds 0.459344 # Number of seconds simulated
-sim_ticks 459344378000 # Number of ticks simulated
-final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.451764 # Number of seconds simulated
+sim_ticks 451764406000 # Number of ticks simulated
+final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78845 # Simulator instruction rate (inst/s)
-host_op_rate 145792 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43799497 # Simulator tick rate (ticks/s)
-host_mem_usage 371908 # Number of bytes of host memory used
-host_seconds 10487.44 # Real time elapsed on the host
+host_inst_rate 99375 # Simulator instruction rate (inst/s)
+host_op_rate 183755 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54293474 # Simulator tick rate (ticks/s)
+host_mem_usage 421524 # Number of bytes of host memory used
+host_seconds 8320.79 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385586 # Number of read requests accepted
-system.physmem.writeReqs 293579 # Number of write requests accepted
-system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386948 # Number of read requests accepted
+system.physmem.writeReqs 294074 # Number of write requests accepted
+system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24063 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26414 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24662 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24515 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23241 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23653 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24406 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24209 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24122 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26505 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24681 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24611 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23302 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23732 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24448 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24311 # Per bank write bursts
system.physmem.perBankRdBursts::8 23620 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23822 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24803 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24074 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23251 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22944 # Per bank write bursts
-system.physmem.perBankRdBursts::14 23767 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23995 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18528 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19811 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18936 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18914 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18031 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18401 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18972 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18946 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18539 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18111 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18827 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17725 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17351 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16948 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17708 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17814 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23937 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24812 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24076 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23393 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22985 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24096 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23981 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18558 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19850 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18948 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18946 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18437 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18993 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18991 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18543 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18160 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18841 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17736 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17380 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16967 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17832 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17826 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 459344352000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 451764392500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 385586 # Read request sizes (log2)
+system.physmem.readPktSize::6 386948 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 293579 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294074 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation
-system.physmem.totQLat 3829490000 # Total ticks spent queuing
-system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks
-system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads
+system.physmem.totQLat 4338654000 # Total ticks spent queuing
+system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.74 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing
-system.physmem.readRowHits 326974 # Number of row buffer hits during reads
-system.physmem.writeRowHits 204419 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes
-system.physmem.avgGap 676336.90 # Average gap between requests
-system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 94627391 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 178768 # Transaction distribution
-system.membus.trans_dist::ReadResp 178768 # Transaction distribution
-system.membus.trans_dist::Writeback 293579 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206818 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206818 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 43466560 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks)
+system.physmem.busUtil 0.75 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 317693 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215552 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes
+system.physmem.avgGap 663362.41 # Average gap between requests
+system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states
+system.physmem.memoryStateTime::REF 15085200000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.membus.trans_dist::ReadReq 179971 # Transaction distribution
+system.membus.trans_dist::ReadResp 179970 # Transaction distribution
+system.membus.trans_dist::Writeback 294074 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206977 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206977 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 860082 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 860082 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.branchPred.lookups 205617659 # Number of BP lookups
-system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 231811700 # Number of BP lookups
+system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 918847215 # number of cpu cycles simulated
+system.cpu.numCycles 903528833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle
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-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued
-system.cpu.iq.rate 1.928766 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued
+system.cpu.iq.rate 2.024408 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed
-system.cpu.iew.exec_branches 167493044 # Number of branches executed
-system.cpu.iew.exec_stores 166813075 # Number of stores executed
-system.cpu.iew.exec_rate 1.907915 # Inst execution rate
-system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1325071563 # num instructions producing a value
-system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value
+system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171944433 # Number of branches executed
+system.cpu.iew.exec_stores 170144104 # Number of stores executed
+system.cpu.iew.exec_rate 2.001031 # Inst execution rate
+system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1369602342 # num instructions producing a value
+system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 355774645 43.17% 43.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 824173639 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
+system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2731132399 # The number of ROB reads
-system.cpu.rob.rob_writes 4012169962 # The number of ROB writes
-system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2860250697 # The number of ROB reads
+system.cpu.rob.rob_writes 4305432555 # The number of ROB writes
+system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
-system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads
-system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3672 # number of floating regfile reads
-system.cpu.fp_regfile_writes 20 # number of floating regfile writes
-system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads
-system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes
-system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads
+system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2763452160 # number of integer regfile reads
+system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes
+system.cpu.fp_regfile_reads 6756 # number of floating regfile reads
+system.cpu.fp_regfile_writes 202 # number of floating regfile writes
+system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads
+system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes
+system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 180976 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 219630492 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3954804981 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 5269 # number of replacements
-system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 7001 # number of replacements
+system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1036.495304 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.506101 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.506101 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 161870260 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 161870260 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 161870260 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 161870260 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 161870260 # number of overall hits
-system.cpu.icache.overall_hits::total 161870260 # number of overall hits
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-system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.tags.sampled_refs 2538610 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 153.151293 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3187 # Occupied blocks per task id
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system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks
-system.cpu.dcache.writebacks::total 2330856 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks
+system.cpu.dcache.writebacks::total 2333034 # number of writebacks
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+system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff