---------- Begin Simulation Statistics ----------
-sim_seconds 0.216744 # Number of seconds simulated
-sim_ticks 216744260000 # Number of ticks simulated
-final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.225207 # Number of seconds simulated
+sim_ticks 225206521000 # Number of ticks simulated
+final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 172626 # Simulator instruction rate (inst/s)
-host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 137034779 # Simulator tick rate (ticks/s)
-host_mem_usage 322768 # Number of bytes of host memory used
-host_seconds 1581.67 # Real time elapsed on the host
-sim_insts 273037857 # Number of instructions simulated
-sim_ops 327812214 # Number of ops (including micro ops) simulated
+host_inst_rate 289736 # Simulator instruction rate (inst/s)
+host_op_rate 347860 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 238979319 # Simulator tick rate (ticks/s)
+host_mem_usage 279872 # Number of bytes of host memory used
+host_seconds 942.37 # Real time elapsed on the host
+sim_insts 273037855 # Number of instructions simulated
+sim_ops 327812212 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7583 # Number of read requests accepted
+system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
+system.physmem.bytes_read::total 485568 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7587 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 630 # Per bank write bursts
-system.physmem.perBankRdBursts::1 843 # Per bank write bursts
+system.physmem.perBankRdBursts::1 846 # Per bank write bursts
system.physmem.perBankRdBursts::2 628 # Per bank write bursts
system.physmem.perBankRdBursts::3 541 # Per bank write bursts
system.physmem.perBankRdBursts::4 466 # Per bank write bursts
-system.physmem.perBankRdBursts::5 348 # Per bank write bursts
-system.physmem.perBankRdBursts::6 173 # Per bank write bursts
+system.physmem.perBankRdBursts::5 349 # Per bank write bursts
+system.physmem.perBankRdBursts::6 171 # Per bank write bursts
system.physmem.perBankRdBursts::7 228 # Per bank write bursts
-system.physmem.perBankRdBursts::8 209 # Per bank write bursts
-system.physmem.perBankRdBursts::9 311 # Per bank write bursts
-system.physmem.perBankRdBursts::10 342 # Per bank write bursts
+system.physmem.perBankRdBursts::8 208 # Per bank write bursts
+system.physmem.perBankRdBursts::9 309 # Per bank write bursts
+system.physmem.perBankRdBursts::10 343 # Per bank write bursts
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
system.physmem.perBankRdBursts::12 553 # Per bank write bursts
-system.physmem.perBankRdBursts::13 706 # Per bank write bursts
-system.physmem.perBankRdBursts::14 637 # Per bank write bursts
-system.physmem.perBankRdBursts::15 540 # Per bank write bursts
+system.physmem.perBankRdBursts::13 705 # Per bank write bursts
+system.physmem.perBankRdBursts::14 639 # Per bank write bursts
+system.physmem.perBankRdBursts::15 543 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 216744023500 # Total gap between requests
+system.physmem.totGap 225206267000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7583 # Read request sizes (log2)
+system.physmem.readPktSize::6 7587 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
-system.physmem.totQLat 54921500 # Total ticks spent queuing
-system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
+system.physmem.totQLat 232471000 # Total ticks spent queuing
+system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6057 # Number of row buffer hits during reads
+system.physmem.readRowHits 6073 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 28582885.86 # Average gap between requests
-system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 29683177.41 # Average gap between requests
+system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.684406 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ)
+system.physmem_0.averagePower 244.071435 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states
+system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.812768 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 33185861 # Number of BP lookups
-system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits
+system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ)
+system.physmem_1.averagePower 245.505361 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 32430299 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 433488520 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 450413042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 273037857 # Number of instructions committed
-system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 273037855 # Number of instructions committed
+system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.587650 # CPI: cycles per instruction
-system.cpu.ipc 0.629862 # IPC: instructions per cycle
-system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 1354 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks.
+system.cpu.cpi 1.649636 # CPI: cycles per instruction
+system.cpu.ipc 0.606194 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction
+system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
+system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction
+system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction
+system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 327812212 # Class of committed instruction
+system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 1355 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits
-system.cpu.dcache.overall_hits::total 168747655 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses
-system.cpu.dcache.overall_misses::total 7285 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits
+system.cpu.dcache.overall_hits::total 168632415 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses
+system.cpu.dcache.overall_misses::total 6945 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 36918 # number of replacements
-system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks.
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.tags.replacements 38188 # number of replacements
+system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits
-system.cpu.icache.overall_hits::total 73120141 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses
-system.cpu.icache.overall_misses::total 38856 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits
+system.cpu.icache.overall_hits::total 69819801 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses
+system.cpu.icache.overall_misses::total 40126 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 38856 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 38856 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 38856 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 38856 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 38856 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668527252 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 668527252 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668527252 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 668527252 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668527252 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 668527252 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.writebacks::writebacks 38188 # number of writebacks
+system.cpu.icache.writebacks::total 38188 # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 4198.154832 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 35803 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 5645 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 6.342427 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 353.729151 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.134287 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 678.291394 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096623 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.128118 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 5645 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172272 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 363531 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 363531 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 35433 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 35433 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 35740 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 35433 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
-system.cpu.l2cache.overall_hits::total 35740 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3423 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 36700 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 37008 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 36700 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits
+system.cpu.l2cache.overall_hits::total 37008 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3423 # number of demand (read+write) misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3426 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 3426 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7627 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3423 # number of overall misses
+system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7627 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 257633750 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105610250 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 363244000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217699750 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 217699750 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 257633750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 323310000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 580943750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 257633750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 323310000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 580943750 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 38856 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 40497 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 38856 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 43367 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 38856 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 43367 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088095 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.117861 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 40126 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 44638 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 40126 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 44638 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088095 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.175871 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088095 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.175871 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75265.483494 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78229.814815 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76103.917871 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76278.819201 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76278.819201 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76169.365412 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75265.483494 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76905.328259 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085381 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085381 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 41 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 41 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3421 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4729 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3424 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3424 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 4729 # Transaction distribution
-system.membus.trans_dist::ReadResp 4729 # Transaction distribution
+system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 4733 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7583 # Request fanout histogram
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 7587 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 7583 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 7587 # Request fanout histogram
+system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff