---------- Begin Simulation Statistics ----------
-sim_seconds 0.068375 # Number of seconds simulated
-sim_ticks 68375005500 # Number of ticks simulated
-final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.068245 # Number of seconds simulated
+sim_ticks 68245472000 # Number of ticks simulated
+final_tick 68245472000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 143200 # Simulator instruction rate (inst/s)
-host_op_rate 183074 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35860683 # Simulator tick rate (ticks/s)
-host_mem_usage 256516 # Number of bytes of host memory used
-host_seconds 1906.68 # Real time elapsed on the host
+host_inst_rate 123424 # Simulator instruction rate (inst/s)
+host_op_rate 157791 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30849723 # Simulator tick rate (ticks/s)
+host_mem_usage 321440 # Number of bytes of host memory used
+host_seconds 2212.19 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory
-system.physmem.bytes_read::total 466432 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 194176 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 194176 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3034 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7288 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2839868 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3981806 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6821674 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2839868 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2839868 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2839868 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3981806 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6821674 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7288 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 7288 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 466432 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 466432 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 802 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 608 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 526 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 353 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 163 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 323 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 416 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 688 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 612 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 506 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 68374814000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 7288 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4427 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2050 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 578 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory
+system.physmem.bytes_read::total 466368 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2839632 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3994053 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6833684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2839632 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2839632 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2839632 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3994053 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6833684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7288 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 7288 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 466432 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 466432 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 606 # Per bank write bursts
+system.physmem.perBankRdBursts::1 802 # Per bank write bursts
+system.physmem.perBankRdBursts::2 608 # Per bank write bursts
+system.physmem.perBankRdBursts::3 526 # Per bank write bursts
+system.physmem.perBankRdBursts::4 441 # Per bank write bursts
+system.physmem.perBankRdBursts::5 356 # Per bank write bursts
+system.physmem.perBankRdBursts::6 162 # Per bank write bursts
+system.physmem.perBankRdBursts::7 220 # Per bank write bursts
+system.physmem.perBankRdBursts::8 205 # Per bank write bursts
+system.physmem.perBankRdBursts::9 290 # Per bank write bursts
+system.physmem.perBankRdBursts::10 324 # Per bank write bursts
+system.physmem.perBankRdBursts::11 417 # Per bank write bursts
+system.physmem.perBankRdBursts::12 531 # Per bank write bursts
+system.physmem.perBankRdBursts::13 687 # Per bank write bursts
+system.physmem.perBankRdBursts::14 611 # Per bank write bursts
+system.physmem.perBankRdBursts::15 502 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 68245446000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 7288 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 4342 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 590 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 718 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 639.554318 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 239.565124 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 1324.415379 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 223 31.06% 31.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 101 14.07% 45.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 63 8.77% 53.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 56 7.80% 61.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 31 4.32% 66.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 32 4.46% 70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 16 2.23% 72.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 24 3.34% 76.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 9 1.25% 77.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 16 2.23% 79.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705 9 1.25% 80.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 12 1.67% 82.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 5 0.70% 83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897 9 1.25% 84.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 7 0.97% 85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 6 0.84% 86.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089 4 0.56% 86.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153 3 0.42% 87.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 5 0.70% 87.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345 3 0.42% 88.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 3 0.42% 89.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473 4 0.56% 89.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601 5 0.70% 90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665 4 0.56% 91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729 3 0.42% 91.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857 3 0.42% 92.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921 1 0.14% 92.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241 2 0.28% 94.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305 1 0.14% 94.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369 1 0.14% 94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561 1 0.14% 94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 718 # Bytes accessed per row activation
-system.physmem.totQLat 36604250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 168483000 # Sum of mem lat for all requests
-system.physmem.totBusLat 36440000 # Total cycles spent in databus access
-system.physmem.totBankLat 95438750 # Total cycles spent in bank access
-system.physmem.avgQLat 5022.54 # Average queueing delay per request
-system.physmem.avgBankLat 13095.33 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 23117.86 # Average memory access latency
-system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 580 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 479.779310 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 274.986956 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 421.744260 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 159 27.41% 27.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 117 20.17% 47.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 45 7.76% 55.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 23 3.97% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 14 2.41% 61.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13 2.24% 63.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6 1.03% 65.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 0.34% 65.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 201 34.66% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 580 # Bytes accessed per row activation
+system.physmem.totQLat 57907000 # Total ticks spent queuing
+system.physmem.totMemAccLat 195684500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 36440000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 101337500 # Total ticks spent accessing banks
+system.physmem.avgQLat 7945.53 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 13904.71 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 26850.23 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 6.83 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 6.83 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6570 # Number of row buffer hits during reads
+system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 5839 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9381835.07 # Average gap between requests
-system.membus.throughput 6821674 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 4467 # Transaction distribution
+system.physmem.avgGap 9364084.25 # Average gap between requests
+system.physmem.pageHitRate 80.12 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 1.16 # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput 6833684 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4468 # Transaction distribution
system.membus.trans_dist::ReadResp 4467 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.membus.trans_dist::ReadExReq 2821 # Transaction distribution
-system.membus.trans_dist::ReadExResp 2821 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14586 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14586 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 466432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 466432 # Total data (bytes)
+system.membus.trans_dist::ReadExReq 2820 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2820 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 466368 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 8910500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 8915000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 68010245 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 67732500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.branchPred.lookups 35388733 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21200896 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1644934 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 19122518 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 16795427 # Number of BTB hits
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 35342667 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21189046 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1621967 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18355176 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 16729462 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 87.830625 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6785564 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 8441 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 91.143021 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 6774978 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 8404 # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 136750012 # number of cpu cycles simulated
+system.cpu.numCycles 136490945 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 38949353 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 317676023 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 35388733 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23580991 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 70834954 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6803690 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21493719 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1383 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37560816 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 509146 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136426737 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.984407 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.454366 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 38825213 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 317051968 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 35342667 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 23504440 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 70679896 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6716000 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 21545367 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 37451719 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 502899 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 136134435 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.985255 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.454681 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66221739 48.54% 48.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6780898 4.97% 53.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5694782 4.17% 57.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6088849 4.46% 62.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4909575 3.60% 65.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4088004 3.00% 68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3182942 2.33% 71.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4139594 3.03% 74.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35320354 25.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66077496 48.54% 48.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6747770 4.96% 53.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5691244 4.18% 57.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6070617 4.46% 62.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4899295 3.60% 65.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4080163 3.00% 68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3177720 2.33% 71.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4131471 3.03% 74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35258659 25.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136426737 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258784 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.323042 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45449120 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16657240 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 66693516 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2548377 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5078484 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7335953 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69077 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 401163284 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 211870 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5078484 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50979253 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1928009 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 329001 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63651330 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14460660 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 393604020 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1657735 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10191603 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 136134435 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258938 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.322879 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45319095 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16701200 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 66547822 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2552537 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5013781 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7320658 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 69067 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 400437341 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 211449 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 5013781 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50843684 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1928767 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 335631 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 63516277 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14496295 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 392925979 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1658279 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10203172 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 22306 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 431444746 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2730832248 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1570013245 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 200164445 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11830 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 36438205 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 103461367 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 91301104 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4273842 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5281559 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 384115412 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 373986631 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1200950 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34324808 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 86133615 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136426737 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.741300 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.023490 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 46878553 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 11940 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11939 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 36493417 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 103352368 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 91160183 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4261604 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5303451 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 383671023 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22900 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 373754233 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1199031 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 33881433 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 97712598 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 780 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 136134435 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.745479 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.022556 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24929928 18.27% 18.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19932793 14.61% 32.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20578448 15.08% 47.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18152288 13.31% 61.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 24038629 17.62% 78.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15699021 11.51% 90.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8799073 6.45% 96.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3376437 2.47% 99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 920120 0.67% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24740289 18.17% 18.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19905513 14.62% 32.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 20515084 15.07% 47.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18158642 13.34% 61.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 24030824 17.65% 78.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15691878 11.53% 90.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8802431 6.47% 96.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3372838 2.48% 99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 916936 0.67% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136426737 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 136134435 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8934 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8938 0.05% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 46301 0.26% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 46049 0.26% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 7704 0.04% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 463 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 190616 1.07% 1.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 3949 0.02% 1.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 241166 1.36% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9286471 52.35% 55.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7950501 44.81% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 3482 0.02% 0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 186470 1.05% 1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 3938 0.02% 1.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241178 1.36% 2.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9277159 52.37% 55.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 7942822 44.84% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 126356667 33.79% 33.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2175742 0.58% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6779199 1.81% 36.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8471128 2.27% 38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3427474 0.92% 39.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1595849 0.43% 39.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20859409 5.58% 45.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7172834 1.92% 47.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127502 1.91% 49.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101548323 27.15% 76.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88297215 23.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 126226981 33.77% 33.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2175715 0.58% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6775957 1.81% 36.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8464752 2.26% 38.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3426733 0.92% 39.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1595441 0.43% 39.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20845390 5.58% 45.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7170609 1.92% 47.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125607 1.91% 49.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101514689 27.16% 76.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88257068 23.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 373986631 # Type of FU issued
-system.cpu.iq.rate 2.734820 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17740799 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047437 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653979183 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 288208067 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 249975124 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 249362565 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 130269118 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118046236 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 263130568 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128596862 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 11091317 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 373754233 # Type of FU issued
+system.cpu.iq.rate 2.738308 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17715164 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047398 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 653197592 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 287339977 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 249810515 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 249359504 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 130249499 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118015221 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 262881293 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 128588104 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 11104968 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8812619 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 109039 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14268 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 8925521 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8703620 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 109542 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14223 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8784600 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 177200 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1779 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 184473 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1790 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5078484 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 284505 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 35417 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 384139745 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 871852 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 103461367 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 91301104 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 311 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 371 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14268 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1284870 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 366093 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1650963 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 370046005 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100262370 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3940626 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5013781 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 291002 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 36408 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 383695470 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 852736 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 103352368 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 91160183 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11866 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 327 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 282 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14223 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1256888 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 362770 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1619658 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 369836414 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100211998 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3917819 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1545 # number of nop insts executed
-system.cpu.iew.exec_refs 187486507 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32007235 # Number of branches executed
-system.cpu.iew.exec_stores 87224137 # Number of stores executed
-system.cpu.iew.exec_rate 2.706003 # Inst execution rate
-system.cpu.iew.wb_sent 368676629 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 368021360 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 182960102 # num instructions producing a value
-system.cpu.iew.wb_consumers 363631500 # num instructions consuming a value
+system.cpu.iew.exec_nop 1547 # number of nop insts executed
+system.cpu.iew.exec_refs 187429987 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31988466 # Number of branches executed
+system.cpu.iew.exec_stores 87217989 # Number of stores executed
+system.cpu.iew.exec_rate 2.709604 # Inst execution rate
+system.cpu.iew.wb_sent 368475660 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 367825736 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 182824140 # num instructions producing a value
+system.cpu.iew.wb_consumers 363330392 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.691198 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.503147 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.694873 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.503190 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 35074746 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 34630475 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1576251 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131348253 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.657554 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.659541 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1553283 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 131120654 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.662167 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.659302 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 34568937 26.32% 26.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 28443468 21.66% 47.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13309150 10.13% 58.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11454276 8.72% 66.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13766870 10.48% 77.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7405227 5.64% 82.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3876233 2.95% 85.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3903284 2.97% 88.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14620808 11.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 34358811 26.20% 26.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 28410916 21.67% 47.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13299289 10.14% 58.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11469684 8.75% 66.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13783827 10.51% 77.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7406623 5.65% 82.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 3875247 2.96% 85.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3903446 2.98% 88.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14612811 11.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131348253 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 131120654 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037337 # Number of instructions committed
system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 14620808 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14612811 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 500864729 # The number of ROB reads
-system.cpu.rob.rob_writes 773362160 # The number of ROB writes
-system.cpu.timesIdled 6666 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 323275 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 500200856 # The number of ROB reads
+system.cpu.rob.rob_writes 772408679 # The number of ROB writes
+system.cpu.timesIdled 6691 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 356510 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273036725 # Number of Instructions Simulated
system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
-system.cpu.cpi 0.500848 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.500848 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.996612 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.996612 # IPC: Total IPC of All Threads
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system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses::total 170866370 # number of overall (read+write) accesses
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+system.cpu.dcache.demand_accesses::total 170794904 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 170794904 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56013.429329 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56013.429329 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55848.079307 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55848.079307 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55873.886547 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55873.886547 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55873.886547 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 25209 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1225 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 407 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.938575 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 102.083333 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59322.972255 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59322.972255 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 26768 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1267 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 424 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.132075 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 97.461538 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1037 # number of writebacks
-system.cpu.dcache.writebacks::total 1037 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2191 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2191 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18581 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18581 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks
+system.cpu.dcache.writebacks::total 1039 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2202 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2202 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 18265 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20772 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20772 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20772 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20772 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4613 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4613 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4613 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4613 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106433039 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 106433039 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 191658495 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298091534 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 298091534 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298091534 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 298091534 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 20467 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20467 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 20467 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 1782 # number of ReadReq MSHR misses
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+system.cpu.dcache.overall_mshr_miss_latency::total 314843789 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60097.706945 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60097.706945 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67437.894089 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67437.894089 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64619.885974 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 64619.885974 # average overall mshr miss latency
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff