---------- Begin Simulation Statistics ----------
-sim_seconds 0.104498 # Number of seconds simulated
-sim_ticks 104497559500 # Number of ticks simulated
-final_tick 104497559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.112541 # Number of seconds simulated
+sim_ticks 112540655000 # Number of ticks simulated
+final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 155883 # Simulator instruction rate (inst/s)
-host_tick_rate 46665641 # Simulator tick rate (ticks/s)
-host_mem_usage 228988 # Number of bytes of host memory used
-host_seconds 2239.28 # Real time elapsed on the host
-sim_insts 349066034 # Number of instructions simulated
-system.physmem.bytes_read 464512 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 192704 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 7258 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 4445195 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1844100 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 4445195 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 123771 # Simulator instruction rate (inst/s)
+host_op_rate 148600 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51015836 # Simulator tick rate (ticks/s)
+host_mem_usage 322668 # Number of bytes of host memory used
+host_seconds 2205.99 # Real time elapsed on the host
+sim_insts 273037219 # Number of instructions simulated
+sim_ops 327811601 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 623680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 9745 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 803 # Per bank write bursts
+system.physmem.perBankRdBursts::1 999 # Per bank write bursts
+system.physmem.perBankRdBursts::2 769 # Per bank write bursts
+system.physmem.perBankRdBursts::3 645 # Per bank write bursts
+system.physmem.perBankRdBursts::4 618 # Per bank write bursts
+system.physmem.perBankRdBursts::5 484 # Per bank write bursts
+system.physmem.perBankRdBursts::6 251 # Per bank write bursts
+system.physmem.perBankRdBursts::7 363 # Per bank write bursts
+system.physmem.perBankRdBursts::8 300 # Per bank write bursts
+system.physmem.perBankRdBursts::9 432 # Per bank write bursts
+system.physmem.perBankRdBursts::10 486 # Per bank write bursts
+system.physmem.perBankRdBursts::11 534 # Per bank write bursts
+system.physmem.perBankRdBursts::12 696 # Per bank write bursts
+system.physmem.perBankRdBursts::13 850 # Per bank write bursts
+system.physmem.perBankRdBursts::14 782 # Per bank write bursts
+system.physmem.perBankRdBursts::15 733 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 112540488500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 9745 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation
+system.physmem.totQLat 248191131 # Total ticks spent queuing
+system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.04 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 8500 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 11548536.53 # Average gap between requests
+system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states
+system.physmem.memoryStateTime::REF 3757780000 # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.membus.trans_dist::ReadReq 9170 # Transaction distribution
+system.membus.trans_dist::ReadResp 9170 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
+system.membus.trans_dist::ReadExReq 575 # Transaction distribution
+system.membus.trans_dist::ReadExResp 575 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 9746 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 9746 # Request fanout histogram
+system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.branchPred.lookups 37763717 # Number of BP lookups
+system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 208995120 # number of cpu cycles simulated
+system.cpu.numCycles 225081311 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 38326507 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21101495 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3258977 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 27386254 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 21276883 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 7682399 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 61114 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 43645867 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 338408122 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 38326507 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 28959282 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 79027162 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 10989913 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 78526305 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 41243030 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 908340 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 208882385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.119969 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.192320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3511516 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130507129 62.48% 62.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 9423807 4.51% 66.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6028759 2.89% 69.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6771553 3.24% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 5439017 2.60% 75.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4859666 2.33% 78.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3802857 1.82% 79.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4240079 2.03% 81.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 37809518 18.10% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 208882385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.183385 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.619215 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 51208963 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 73647751 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 72596931 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3816657 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 7612083 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7463930 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 71162 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 431701457 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 197547 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 7612083 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 58859623 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1188483 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 57604104 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 68958235 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14659857 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 416634975 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8024802 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 455431964 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2446622850 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1351809132 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1094813718 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 70863365 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3987641 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4044473 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 48252141 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 108792162 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 93099672 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3342545 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2273908 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 394239255 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3865155 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 379120981 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1801347 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 46369193 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 143590674 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 309514 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 208882385 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.814997 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.995935 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 82049002 39.28% 39.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 34801326 16.66% 55.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24478546 11.72% 67.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18529016 8.87% 76.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21712805 10.39% 86.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15357191 7.35% 94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8402907 4.02% 98.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2691838 1.29% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 859754 0.41% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 208882385 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2250 0.01% 0.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 10815 0.06% 0.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 2509 0.01% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 64370 0.37% 0.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 177500 1.02% 1.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9658261 55.66% 57.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7430721 42.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 129606192 34.19% 34.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2147281 0.57% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6746387 1.78% 36.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8673518 2.29% 38.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3499070 0.92% 39.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1584810 0.42% 40.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 21149805 5.58% 45.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7187648 1.90% 47.64% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147289 1.89% 49.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103746274 27.36% 76.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 87457408 23.07% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 379120981 # Type of FU issued
-system.cpu.iq.rate 1.814018 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17352648 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.045771 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 735350759 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 310614656 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 251531674 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 250927583 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 133866908 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118270115 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 267600383 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128873246 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7282081 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued
+system.cpu.iq.rate 1.538412 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 14143162 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 112354 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 8279 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10723841 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 272 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 7612083 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 19341 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 398151655 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 2633597 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 108792162 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 93099672 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3853935 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 8279 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3193235 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 309338 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3502573 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 373031388 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 102121270 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6089593 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 47245 # number of nop insts executed
-system.cpu.iew.exec_refs 188074720 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32215232 # Number of branches executed
-system.cpu.iew.exec_stores 85953450 # Number of stores executed
-system.cpu.iew.exec_rate 1.784881 # Inst execution rate
-system.cpu.iew.wb_sent 370805637 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 369801789 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 175613931 # num instructions producing a value
-system.cpu.iew.wb_consumers 345608979 # num instructions consuming a value
+system.cpu.iew.exec_nop 864 # number of nop insts executed
+system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31752179 # Number of branches executed
+system.cpu.iew.exec_stores 84582729 # Number of stores executed
+system.cpu.iew.exec_rate 1.520806 # Inst execution rate
+system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 153543382 # num instructions producing a value
+system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.769428 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.508129 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 49085191 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 3229927 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 201270303 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.734318 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.320939 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 89873146 44.65% 44.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 39586205 19.67% 64.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 17962686 8.92% 73.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 13145817 6.53% 79.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 14573998 7.24% 87.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7584463 3.77% 90.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3507612 1.74% 92.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3437369 1.71% 94.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11599007 5.76% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 201270303 # Number of insts commited each cycle
-system.cpu.commit.count 349066646 # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 273037831 # Number of instructions committed
+system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 177024831 # Number of memory references committed
-system.cpu.commit.loads 94649000 # Number of loads committed
+system.cpu.commit.refs 168107892 # Number of memory references committed
+system.cpu.commit.loads 85732275 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
-system.cpu.commit.branches 30521879 # Number of branches committed
+system.cpu.commit.branches 30563525 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
+system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 11599007 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
+system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 587820610 # The number of ROB reads
-system.cpu.rob.rob_writes 803918901 # The number of ROB writes
-system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 112735 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 349066034 # Number of Instructions Simulated
-system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
-system.cpu.cpi 0.598727 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.598727 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.670211 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.670211 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1781871579 # number of integer regfile reads
-system.cpu.int_regfile_writes 235815438 # number of integer regfile writes
-system.cpu.fp_regfile_reads 188771754 # number of floating regfile reads
-system.cpu.fp_regfile_writes 133861667 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1003473737 # number of misc regfile reads
-system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
-system.cpu.icache.replacements 14107 # number of replacements
-system.cpu.icache.tagsinuse 1842.677380 # Cycle average of tags in use
-system.cpu.icache.total_refs 41226387 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15987 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2578.744417 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1842.677380 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.899745 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 41226387 # number of ReadReq hits
-system.cpu.icache.demand_hits 41226387 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 41226387 # number of overall hits
-system.cpu.icache.ReadReq_misses 16643 # number of ReadReq misses
-system.cpu.icache.demand_misses 16643 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 16643 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 201090500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 201090500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 201090500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 41243030 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 41243030 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 41243030 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12082.587274 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12082.587274 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12082.587274 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 561656707 # The number of ROB reads
+system.cpu.rob.rob_writes 705358338 # The number of ROB writes
+system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 273037219 # Number of Instructions Simulated
+system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 331187238 # number of integer regfile reads
+system.cpu.int_regfile_writes 136909181 # number of integer regfile writes
+system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads
+system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes
+system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads
+system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes
+system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads
+system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 50213 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
+system.cpu.icache.tags.replacements 715368 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits
+system.cpu.icache.overall_hits::total 88391816 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses
+system.cpu.icache.overall_misses::total 719790 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 16006 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 16006 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 16006 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 136032000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 136032000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 136032000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 8498.812945 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1408 # number of replacements
-system.cpu.dcache.tagsinuse 3101.194672 # Cycle average of tags in use
-system.cpu.dcache.total_refs 176614084 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 38427.781549 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 3101.194672 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.757128 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 94558380 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 82033210 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 11361 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 176591590 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 176591590 # number of overall hits
-system.cpu.dcache.ReadReq_misses 3380 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 19484 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 22864 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 22864 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 111762500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 649531500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 761294000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 761294000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 94561760 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 11363 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 176614454 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 176614454 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33296.623513 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33296.623513 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1030 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 16619 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 18249 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 18249 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 2865 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 4615 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 4615 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 53437000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 101725000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 155162000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 155162000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 57 # number of replacements
-system.cpu.l2cache.tagsinuse 3897.011564 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13334 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 5354 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.490474 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 3518.810301 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 378.201262 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.107386 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.011542 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 13251 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 1030 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements 1533746 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits
+system.cpu.dcache.overall_hits::total 163781573 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses
+system.cpu.dcache.overall_misses::total 3771680 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks
+system.cpu.dcache.writebacks::total 966282 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff