stats: update stats for cache occupancy and clock domain changes

[gem5.git] / tests / long / se / 40.perlbmk / ref / alpha / tru64 / simple-atomic / config.ini

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index a895468a4f8923a0f1e7f4db7be0258f785483b1..3b24ee76950c11b1a1d76a4903c9743defe367a8 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,17 +1,29 @@
 [root]
 type=Root
 children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -19,57 +31,85 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
-phase=0
+profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -80,23 +120,38 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
 [system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
+type=CoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
+system=system
 use_default_range=false
-width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
-file=
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000