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-host_inst_rate 1954286 # Simulator instruction rate (inst/s)
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff