stats: update references
[gem5.git] / tests / long / se / 40.perlbmk / ref / arm / linux / minor-timing / stats.txt
index 228ad0113a7237e22f5c566b9cfd625e2fa7b000..d38edd9f8e89db9b2cc4a9f00eca7bb8493612d2 100644 (file)
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.512877                       # Number of seconds simulated
-sim_ticks                                512876814500                       # Number of ticks simulated
-final_tick                               512876814500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.525654                       # Number of seconds simulated
+sim_ticks                                525654485500                       # Number of ticks simulated
+final_tick                               525654485500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169706                       # Simulator instruction rate (inst/s)
-host_op_rate                                   208931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              135858559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 281524                       # Number of bytes of host memory used
-host_seconds                                  3775.08                       # Real time elapsed on the host
+host_inst_rate                                 213828                       # Simulator instruction rate (inst/s)
+host_op_rate                                   263250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              175444467                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278324                       # Number of bytes of host memory used
+host_seconds                                  2996.13                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            164160                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          18474496                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             18638656                       # Number of bytes read from this memory
@@ -26,64 +26,64 @@ system.physmem.num_reads::cpu.data             288664                       # Nu
 system.physmem.num_reads::total                291229                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               320077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36021312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36341389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          320077                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             320077                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8248125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8248125                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8248125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              320077                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36021312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               44589514                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               312296                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35145702                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                35457999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          312296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             312296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8047628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8047628                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8047628                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              312296                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35145702                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               43505627                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        291229                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
 system.physmem.readBursts                      291229                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18616640                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22016                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                 18617024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21632                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4229248                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  18638656                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      344                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      338                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18285                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18130                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18177                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18281                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18133                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18221                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18176                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18285                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18413                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18173                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17985                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18026                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18055                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18102                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18206                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18274                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18073                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18262                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18412                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18178                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18034                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18056                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18101                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18200                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18218                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4135                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    512876719500                       # Total gap between requests
+system.physmem.totGap                    525654384500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290520                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       355                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290516                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      889                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     4011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4015                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -194,91 +194,101 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       110420                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      206.874986                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.678155                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     257.334201                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45202     40.94%     40.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43704     39.58%     80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9014      8.16%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2046      1.85%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          604      0.55%     91.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          569      0.52%     91.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          621      0.56%     92.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          527      0.48%     92.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8133      7.37%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         110420                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4015                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.540971                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.171361                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.693530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4013     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       102767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      222.307005                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     147.372317                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     261.848294                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          36138     35.16%     35.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41898     40.77%     75.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13163     12.81%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1012      0.98%     89.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          489      0.48%     90.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1030      1.00%     91.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          399      0.39%     91.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          484      0.47%     92.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8154      7.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         102767                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4019                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.497387                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.151985                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.429034                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4017     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4015                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.455293                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.434809                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.838731                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3101     77.24%     77.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                914     22.76%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4015                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2756382250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8210476000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454425000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9475.85                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4019                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4019                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.442399                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.422334                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.830212                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3130     77.88%     77.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                889     22.12%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4019                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15538679500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               20992885750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454455000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       53417.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28225.85                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.30                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           8.24                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        8.25                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  72167.53                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          35.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.05                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       35.46                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.35                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.34                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.28                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194946                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51576                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   67.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1435314.77                       # Average gap between requests
-system.physmem.pageHitRate                      69.06                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  418362840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  228273375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1136124600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            33498338640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           103989168945                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           216505087500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             355990887180                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              694.111511                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   359471319000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     17125940000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    136275516000                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  416336760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  227167875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132396200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212589360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            33498338640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           103752790515                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           216712437000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             355952056350                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              694.035798                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   359820444250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     17125940000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    135926935750                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups               147261658                       # Number of BP lookups
+system.physmem.avgWrQLen                        19.65                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202495                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51707                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1471073.79                       # Average gap between requests
+system.physmem.pageHitRate                      71.21                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  367124520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  195116130                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1040126640                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                173653740                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           28870255440.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             8266537290                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             1634065440                       # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy       57360982710                       # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy       51276223200                       # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy        64953258915                       # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy             214157919585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              407.411950                       # Core power per rank (mW)
+system.physmem_0.totalIdleTime           503225172750                       # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE     3206676000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12282762000                       # Time in different power states
+system.physmem_0.memoryStateTime::SREF   243901523000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 133531907000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      6939814000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 125791803500                       # Time in different power states
+system.physmem_1.actEnergy                  366660420                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  194884635                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1036835100                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                171294300                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           28737493200.000008                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             8178131430                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             1630074720                       # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy       56926536120                       # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy       51134645280                       # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy        65306601210                       # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy             213703234155                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              406.546781                       # Core power per rank (mW)
+system.physmem_1.totalIdleTime           503430400500                       # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE     3200172000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12226116000                       # Time in different power states
+system.physmem_1.memoryStateTime::SREF   245428473250                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 133163073250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      6797797000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 124838854000                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups               147261657                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          98231058                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1384734                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             89949366                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                63294628                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             89949365                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                63294627                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             70.366953                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                19276105                       # Number of times the RAS was used to get a target.
@@ -288,7 +298,7 @@ system.cpu.branchPred.indirectHits           15988941                       # Nu
 system.cpu.branchPred.indirectMisses             6214                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted      1280093                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -318,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -348,7 +358,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -378,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -409,16 +419,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                       1025753629                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                       1051308971                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       8621768                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       8621767                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.601101                       # CPI: cycles per instruction
-system.cpu.ipc                               0.624570                       # IPC: instructions per cycle
+system.cpu.cpi                               1.640991                       # CPI: cycles per instruction
+system.cpu.ipc                               0.609388                       # IPC: instructions per cycle
 system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
 system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
 system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
@@ -454,28 +464,28 @@ system.cpu.op_class_0::MemWrite             128980497     16.35%    100.00% # Cl
 system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
 system.cpu.op_class_0::total                788730744                       # Class of committed instruction
-system.cpu.tickCycles                       955906199                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        69847430                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles                       955911046                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        95397925                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            778100                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.223033                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4092.108689                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378449407                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782196                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.829382                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         804340500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.223033                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999078                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999078                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle         850386500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.108689                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999050                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999050                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1421                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1501                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          970                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         759383100                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        759383100                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    249620680                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       249620680                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
@@ -500,14 +510,14 @@ system.cpu.dcache.demand_misses::cpu.data       850904                       # n
 system.cpu.dcache.demand_misses::total         850904                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       851045                       # number of overall misses
 system.cpu.dcache.overall_misses::total        851045                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24857030500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24857030500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10252359000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10252359000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35109389500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35109389500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35109389500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35109389500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37269485500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37269485500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10946218000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10946218000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  48215703500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  48215703500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  48215703500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  48215703500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250333872                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250333872                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -532,14 +542,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002243
 system.cpu.dcache.demand_miss_rate::total     0.002243                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002244                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002244                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41261.281531                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41254.445417                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56664.093129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56654.705098                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -566,16 +576,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782057
 system.cpu.dcache.demand_mshr_misses::total       782057                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782196                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782196                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24135855500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24135855500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5141186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5141186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1790000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1790000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29277041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29277041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29278831500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29278831500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  36547770500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  36547770500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5489520000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5489520000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1802000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  42037290500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  42037290500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  42039092500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  42039092500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -586,70 +596,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             24885                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1711.965016                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           257789646                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1711.889727                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           257789639                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             26636                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           9678.241703                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9678.241440                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1711.965016                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.835920                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.835920                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1711.889727                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.835884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.835884                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1596                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         515659202                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        515659202                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst    257789646                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       257789646                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     257789646                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        257789646                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    257789646                       # number of overall hits
-system.cpu.icache.overall_hits::total       257789646                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         515659188                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        515659188                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst    257789639                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       257789639                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     257789639                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        257789639                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    257789639                       # number of overall hits
+system.cpu.icache.overall_hits::total       257789639                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        26637                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         26637                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        26637                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          26637                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        26637                       # number of overall misses
 system.cpu.icache.overall_misses::total         26637                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    518689000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    518689000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    518689000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    518689000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    518689000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    518689000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    257816283                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    257816283                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    257816283                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    257816283                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    257816283                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    257816283                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    539890500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    539890500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    539890500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    539890500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    539890500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    539890500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    257816276                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    257816276                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    257816276                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    257816276                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    257816276                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    257816276                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000103                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000103                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000103                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000103                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000103                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000103                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19472.500657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19472.500657                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20268.442392                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20268.442392                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -664,48 +674,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        26637
 system.cpu.icache.demand_mshr_misses::total        26637                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        26637                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        26637                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    492053000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    492053000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    492053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    492053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    492053000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    492053000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    513254500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    513254500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    513254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    513254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    513254500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    513254500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000103                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000103                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000103                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000103                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           258837                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32655.350813                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        32651.524409                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1316948                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           291605                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.516205                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       3732066000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    41.642986                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    88.982590                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.001271                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002716                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.992576                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996562                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.warmup_cycle       3958369000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    41.514151                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    89.268254                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.001267                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.992454                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996445                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          308                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2976                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2912                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29221                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         13160277                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        13160277                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks        88688                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total        88688                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        23552                       # number of WritebackClean hits
@@ -734,18 +744,18 @@ system.cpu.l2cache.demand_misses::total        291260                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2570                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       288690                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       291260                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5003275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5003275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    198116500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    198116500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17918475000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17918475000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    198116500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22921750000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23119866500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    198116500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22921750000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23119866500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5351609000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5351609000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    219318000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    219318000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30330402000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  30330402000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    219318000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35682011000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35901329000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    219318000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35682011000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35901329000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks        88688                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total        88688                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        23552                       # number of WritebackClean accesses(hits+misses)
@@ -774,18 +784,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.360099                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096482                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.369076                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.360099                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -816,18 +826,18 @@ system.cpu.l2cache.demand_mshr_misses::total       291230
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2566                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       288664                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       291230                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4342365000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4342365000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    172194500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    172194500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15690918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15690918500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    172194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20033283500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20205478000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    172194500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20033283500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20205478000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4690699000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4690699000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193386000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193386000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  28102659500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  28102659500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193386000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32793358500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  32986744500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193386000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32793358500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  32986744500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096332                       # mshr miss rate for ReadCleanReq accesses
@@ -840,25 +850,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.360062
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096332                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.369043                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.360062                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests      1611818                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       803044                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3234                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2036                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2021                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        739510                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       154786                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        24885                       # Transaction distribution
@@ -898,7 +908,7 @@ system.membus.snoop_filter.hit_multi_requests            0
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500                       # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp             225138                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           190702                       # Transaction distribution
@@ -921,9 +931,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              291229                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           917201000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           917205000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554703000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1553500250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------