stats: update stale config.ini files, eio and few other stats.

[gem5.git] / tests / long / se / 40.perlbmk / ref / arm / linux / o3-timing / config.ini

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 3db3f48e914d913f3e9fb32767c6dd13d7877f6d..2898b2e5157b2bcfa8eaa94465693bbbb7a2e053 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -23,6 +23,7 @@ load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -135,7 +136,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=BiModeBP
 BTBEntries=2048
 BTBTagSize=18
 RASSize=16
@@ -145,11 +146,7 @@ eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
 numThreads=1
-predType=bi-mode
 
 [system.cpu.dcache]
 type=BaseCache
@@ -157,10 +154,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -171,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -191,6 +188,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.dtb
 
 [system.cpu.dstage2_mmu.stage2_tlb]
@@ -208,7 +206,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -243,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -257,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -285,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -299,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -313,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
 type=BaseCache
@@ -498,10 +495,11 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
-forward_snoops=true
+forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -512,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -558,6 +555,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -565,6 +563,7 @@ type=ArmStage2MMU
 children=stage2_tlb
 eventq_index=0
 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
 tlb=system.cpu.itb
 
 [system.cpu.istage2_mmu.stage2_tlb]
@@ -582,7 +581,6 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.itb]
 type=ArmTLB
@@ -607,10 +605,11 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -621,26 +620,33 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu.l2cache.tags]
@@ -657,13 +663,16 @@ size=1048576
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -673,14 +682,16 @@ eventq_index=0
 type=LiveProcess
 cmd=perlbmk -I. -I lib mdred.makerand.pl
 cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+drivers=
 egid=100
 env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -710,11 +721,14 @@ transition_latency=100000000
 type=CoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
@@ -745,7 +759,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -754,6 +768,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0