---------- Begin Simulation Statistics ----------
-sim_seconds 0.640648 # Number of seconds simulated
-sim_ticks 640648369500 # Number of ticks simulated
-final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.629535 # Number of seconds simulated
+sim_ticks 629535413500 # Number of ticks simulated
+final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107808 # Simulator instruction rate (inst/s)
-host_op_rate 146820 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49890421 # Simulator tick rate (ticks/s)
-host_mem_usage 251704 # Number of bytes of host memory used
-host_seconds 12841.11 # Real time elapsed on the host
+host_inst_rate 71307 # Simulator instruction rate (inst/s)
+host_op_rate 97111 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32426577 # Simulator tick rate (ticks/s)
+host_mem_usage 303200 # Number of bytes of host memory used
+host_seconds 19414.18 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474992 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 66098 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 474992 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 66098 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 30399488 # Total number of bytes read from memory
-system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 640648293500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 474992 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 66098 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see
+system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 474963 # Number of read requests accepted
+system.physmem.writeReqs 66098 # Number of write requests accepted
+system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 29871 # Per bank write bursts
+system.physmem.perBankRdBursts::1 29675 # Per bank write bursts
+system.physmem.perBankRdBursts::2 29749 # Per bank write bursts
+system.physmem.perBankRdBursts::3 29712 # Per bank write bursts
+system.physmem.perBankRdBursts::4 29816 # Per bank write bursts
+system.physmem.perBankRdBursts::5 29834 # Per bank write bursts
+system.physmem.perBankRdBursts::6 29642 # Per bank write bursts
+system.physmem.perBankRdBursts::7 29444 # Per bank write bursts
+system.physmem.perBankRdBursts::8 29480 # Per bank write bursts
+system.physmem.perBankRdBursts::9 29489 # Per bank write bursts
+system.physmem.perBankRdBursts::10 29547 # Per bank write bursts
+system.physmem.perBankRdBursts::11 29649 # Per bank write bursts
+system.physmem.perBankRdBursts::12 29701 # Per bank write bursts
+system.physmem.perBankRdBursts::13 29813 # Per bank write bursts
+system.physmem.perBankRdBursts::14 29629 # Per bank write bursts
+system.physmem.perBankRdBursts::15 29799 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
+system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4138 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4148 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4226 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
+system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 629535350500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 474963 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 66098 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation
-system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2374200000 # Total cycles spent in databus access
-system.physmem.totBankLat 10704210000 # Total cycles spent in bank access
-system.physmem.avgQLat 3976.96 # Average queueing delay per request
-system.physmem.avgBankLat 22542.77 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31519.74 # Average memory access latency
-system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.42 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 17.45 # Average write queue length over time
-system.physmem.readRowHits 318007 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49644 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
-system.physmem.avgGap 1183995.81 # Average gap between requests
-system.membus.throughput 54054139 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 408917 # Transaction distribution
-system.membus.trans_dist::ReadResp 408916 # Transaction distribution
+system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation
+system.physmem.totQLat 3804882250 # Total ticks spent queuing
+system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks
+system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.43 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing
+system.physmem.readRowHits 300749 # Number of row buffer hits during reads
+system.physmem.writeRowHits 49371 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes
+system.physmem.avgGap 1163520.10 # Average gap between requests
+system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput 55005389 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408886 # Transaction distribution
+system.membus.trans_dist::ReadResp 408885 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
-system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
-system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024803 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1024803 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 34629696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34629696 # Total data (bytes)
+system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66077 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66077 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34627840 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.cpu.branchPred.lookups 451070712 # Number of BP lookups
-system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits
+system.cpu.branchPred.lookups 438247561 # Number of BP lookups
+system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1281296740 # number of cpu cycles simulated
+system.cpu.numCycles 1259070828 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued
-system.cpu.iq.rate 1.917842 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued
+system.cpu.iq.rate 1.934087 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12463 # number of nop insts executed
-system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed
-system.cpu.iew.exec_branches 324680497 # Number of branches executed
-system.cpu.iew.exec_stores 426903851 # Number of stores executed
-system.cpu.iew.exec_rate 1.856653 # Inst execution rate
-system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1354756756 # num instructions producing a value
-system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value
+system.cpu.iew.exec_nop 12446 # number of nop insts executed
+system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed
+system.cpu.iew.exec_branches 319532182 # Number of branches executed
+system.cpu.iew.exec_stores 423276586 # Number of stores executed
+system.cpu.iew.exec_rate 1.874346 # Inst execution rate
+system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1349155886 # num instructions producing a value
+system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
-system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
-system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3791959297 # The number of ROB reads
+system.cpu.rob.rob_writes 5711929091 # The number of ROB writes
+system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
-system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
+system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads
+system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52387 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178835 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3231222 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1536768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104525120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 106061888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.tags.replacements 22329 # number of replacements
-system.cpu.icache.tags.tagsinuse 1638.931929 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 345969528 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 24011 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 14408.792970 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 23332 # number of replacements
+system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1638.931929 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.800260 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.800260 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 345973619 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 345973619 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 345973619 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 345973619 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 345973619 # number of overall hits
-system.cpu.icache.overall_hits::total 345973619 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 30537 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 30537 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 30537 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 30537 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 30537 # number of overall misses
-system.cpu.icache.overall_misses::total 30537 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 527751245 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 527751245 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 527751245 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 527751245 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 527751245 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 527751245 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 346004156 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 346004156 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 346004156 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 346004156 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 346004156 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 346004156 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17282.354030 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17282.354030 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1734 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits
+system.cpu.icache.overall_hits::total 334702534 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses
+system.cpu.icache.overall_misses::total 32107 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 54.187500 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2162 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2162 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2162 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2162 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2162 # number of overall MSHR hits
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+system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks
-system.cpu.dcache.writebacks::total 96304 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks
+system.cpu.dcache.writebacks::total 96313 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff