---------- Begin Simulation Statistics ----------
-sim_seconds 0.627778 # Number of seconds simulated
-sim_ticks 627777658000 # Number of ticks simulated
-final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.338999 # Number of seconds simulated
+sim_ticks 338998876000 # Number of ticks simulated
+final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109787 # Simulator instruction rate (inst/s)
-host_op_rate 149515 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49785649 # Simulator tick rate (ticks/s)
-host_mem_usage 262368 # Number of bytes of host memory used
-host_seconds 12609.61 # Real time elapsed on the host
-sim_insts 1384370590 # Number of instructions simulated
-sim_ops 1885325342 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474966 # Total number of read requests seen
-system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30397824 # Total number of bytes read from memory
-system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 627777588500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 474966 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 66098 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+host_inst_rate 210128 # Simulator instruction rate (inst/s)
+host_op_rate 258696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 111189218 # Simulator tick rate (ticks/s)
+host_mem_usage 277020 # Number of bytes of host memory used
+host_seconds 3048.85 # Real time elapsed on the host
+sim_insts 640649299 # Number of instructions simulated
+sim_ops 788724958 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory
+system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory
+system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 956909 # Number of read requests accepted
+system.physmem.writeReqs 66317 # Number of write requests accepted
+system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 19928 # Per bank write bursts
+system.physmem.perBankRdBursts::1 19580 # Per bank write bursts
+system.physmem.perBankRdBursts::2 657267 # Per bank write bursts
+system.physmem.perBankRdBursts::3 20958 # Per bank write bursts
+system.physmem.perBankRdBursts::4 19729 # Per bank write bursts
+system.physmem.perBankRdBursts::5 20737 # Per bank write bursts
+system.physmem.perBankRdBursts::6 19560 # Per bank write bursts
+system.physmem.perBankRdBursts::7 19988 # Per bank write bursts
+system.physmem.perBankRdBursts::8 19522 # Per bank write bursts
+system.physmem.perBankRdBursts::9 20089 # Per bank write bursts
+system.physmem.perBankRdBursts::10 19525 # Per bank write bursts
+system.physmem.perBankRdBursts::11 19708 # Per bank write bursts
+system.physmem.perBankRdBursts::12 19661 # Per bank write bursts
+system.physmem.perBankRdBursts::13 21032 # Per bank write bursts
+system.physmem.perBankRdBursts::14 19553 # Per bank write bursts
+system.physmem.perBankRdBursts::15 19787 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4255 # Per bank write bursts
+system.physmem.perBankWrBursts::1 4105 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4143 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4152 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4244 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4226 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4097 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
+system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4152 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 338998865500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 956909 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 66317 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2374030000 # Total cycles spent in databus access
-system.physmem.totBankLat 15605933750 # Total cycles spent in bank access
-system.physmem.avgQLat 6703.42 # Average queueing delay per request
-system.physmem.avgBankLat 32868.02 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 44571.44 # Average memory access latency
-system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.43 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 17.42 # Average write queue length over time
-system.physmem.readRowHits 143321 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45521 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes
-system.physmem.avgGap 1160264.94 # Average gap between requests
-system.cpu.branchPred.lookups 438315942 # Number of BP lookups
-system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads
+system.physmem.totQLat 27417238749 # Total ticks spent queuing
+system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 1.51 # Data bus utilization in percentage
+system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing
+system.physmem.readRowHits 804753 # Number of row buffer hits during reads
+system.physmem.writeRowHits 22823 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes
+system.physmem.avgGap 331304.00 # Average gap between requests
+system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ)
+system.physmem_0.averagePower 558.898453 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states
+system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states
+system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ)
+system.physmem_1.averagePower 480.731167 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states
+system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 174659469 # Number of BP lookups
+system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1255555317 # number of cpu cycles simulated
+system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 677997753 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued
-system.cpu.iq.rate 1.941304 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued
+system.cpu.iq.rate 1.268482 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12468 # number of nop insts executed
-system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed
-system.cpu.iew.exec_branches 322574286 # Number of branches executed
-system.cpu.iew.exec_stores 423720930 # Number of stores executed
-system.cpu.iew.exec_rate 1.882449 # Inst execution rate
-system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347631579 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value
-system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 10143 # number of nop insts executed
+system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed
+system.cpu.iew.exec_branches 143380865 # Number of branches executed
+system.cpu.iew.exec_stores 152688992 # Number of stores executed
+system.cpu.iew.exec_rate 1.253946 # Inst execution rate
+system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 486195731 # num instructions producing a value
+system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
-system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 640654411 # Number of instructions committed
+system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 908382478 # Number of memory references committed
-system.cpu.commit.loads 631387181 # Number of loads committed
-system.cpu.commit.membars 9986 # Number of memory barriers committed
-system.cpu.commit.branches 299634395 # Number of branches committed
-system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
-system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3802578575 # The number of ROB reads
-system.cpu.rob.rob_writes 5740389473 # The number of ROB writes
-system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
-system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads
-system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads
-system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.icache.replacements 22740 # number of replacements
-system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use
-system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits
-system.cpu.icache.overall_hits::total 333090004 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses
-system.cpu.icache.overall_misses::total 31630 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 442184 # number of replacements
-system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks.
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 552356 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 955532 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution
+system.membus.trans_dist::CleanEvict 230803 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1375 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1375 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 957090 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 957090 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / blobdiff