-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.058730 # Number of seconds simulated
-sim_ticks 58730125500 # Number of ticks simulated
-final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 197162 # Simulator instruction rate (inst/s)
-host_op_rate 252141 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 163284235 # Simulator tick rate (ticks/s)
-host_mem_usage 321164 # Number of bytes of host memory used
-host_seconds 359.68 # Real time elapsed on the host
-sim_insts 70915127 # Number of instructions simulated
-sim_ops 90690083 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128871 # Number of read requests accepted
-system.physmem.writeReqs 83951 # Number of write requests accepted
-system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 8159 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8376 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8228 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8171 # Per bank write bursts
-system.physmem.perBankRdBursts::4 8319 # Per bank write bursts
-system.physmem.perBankRdBursts::5 8450 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8088 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7640 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7818 # Per bank write bursts
-system.physmem.perBankRdBursts::11 7832 # Per bank write bursts
-system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7879 # Per bank write bursts
-system.physmem.perBankRdBursts::14 7977 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8007 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5180 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
-system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
-system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
-system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5197 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5050 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5087 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5227 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58730091000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 128871 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 83951 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads
-system.physmem.totQLat 1533027250 # Total ticks spent queuing
-system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.81 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
-system.physmem.readRowHits 112070 # Number of row buffer hits during reads
-system.physmem.writeRowHits 62147 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes
-system.physmem.avgGap 275958.74 # Average gap between requests
-system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ)
-system.physmem_0.averagePower 708.329716 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ)
-system.physmem_1.averagePower 706.358131 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 14827059 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 117460251 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 70915127 # Number of instructions committed
-system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.656350 # CPI: cycles per instruction
-system.cpu.ipc 0.603737 # IPC: instructions per cycle
-system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 156434 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits
-system.cpu.dcache.overall_hits::total 42634623 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses
-system.cpu.dcache.overall_misses::total 262226 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks
-system.cpu.dcache.writebacks::total 128445 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 42774 # number of replacements
-system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits
-system.cpu.icache.overall_hits::total 25093452 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses
-system.cpu.icache.overall_misses::total 44817 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id
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-system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
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-system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram
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-system.membus.trans_dist::ReadResp 26591 # Transaction distribution
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-system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
projects / gem5.git / blobdiff